€¬ÀpX|o?ÿ?€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€Set SRAM to 1.1V... Read SRAM1 = 0xB0B0B0B... Read SRAM2 = 0xB0B0B0B... Read SRAM2 CTRL6= 0x88888888... Pll init start... mtcmos Start.. mtcmos Done! Pll init Done! USB PRB0 LineState: 0 [U] USB cable/ No Cable inserted! [PLFM] Keep stay in USB Mode [PWRAP] pwrap_init_preloader [PWRAP] Preloader pwrap_init start!!!!!!!!!!!!! [PWRAP] Dump PD_CFG0=0x0 ([10]=MI,[11]=MO, [12]=CK, [13]=CSN), [PWRAP] Dump PU_CFG0=0x0 ([10]=MI,[11]=MO, [12]=CK, [13]=CSN), [PWRAP] SMT setting is OK.[PWRAP] DRV setting is OK.[PWRAP] slave IO setting is OK.[PWRAP] start reset wrapper [PWRAP] pwrap_init---- reset ok [PWRAP] spi clk set .... [PWRAP] pwrap_init---- clk set ok [PWRAP] pwrap_init---- dcm enable [PWRAP] pwrap_init---- slave reset ok [PWRAP] pwrap_init---- wacs2 enable ok [PWRAP] pwrap_init---- debug: init_reg_clock ok [PWRAP] pwrap_init---- debug: init_dio ok [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=0 rdata=6886 at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=1 rdata=E55A at times=11 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=2 rdata=E55A at times=11 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=3 rdata=E55A at times=11 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=8 rdata=A21A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=9 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=10 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=11 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=12 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=13 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=14 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=15 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=16 rdata=886A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=17 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=18 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=19 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe best point,at index=7 [PWRAP] pwrap_init---- strobe ok [PWRAP] mt_pwrap_init---- init_chiper1 [PWRAP] mt_pwrap_init---- init_chiper2 [PWRAP] mt_pwrap_init---- init_chiper3 [PWRAP] pwrap_init---- Cipher ok [PWRAP] pwrap_init---- adc_set ok [PWRAP] pwrap_init---- priority ok [PWRAP] pwrap_init---- wacs enable ok [PWRAP] Preloader PMIC_WRAP_WACS_P2P_EN=1 [PWRAP] Preloader PMIC_WRAP_INIT_DONE_P2P=1 [PWRAP] Preloader pwrap_init Done!!!!!!!!! [PWRAP] after MT6351 pwrap_write [PWRAP] write MT6351 Test pass [PWRAP] Read MT6351 Test pass,return_value=0 [PMIC_WRAP]wrap_init pass,the return value=0. DATE_CODE_YY:0, DATE_CODE_WW:0 [SegCode] CS, PROJECT_CODE:0x1A8D, FUNCTION_CODE_0:0x0, FUNCTION_CODE_1:0x0, FAB_CODE:0x0 [LDO] 0:0x8979AB79, 1:0x0, 2:0x78A90000, 3:0xBA999 [PMIC_PRELOADER] Preloader Start.................. [PMIC_PRELOADER] MT6351 CHIP Code = 0x5120 [PMIC_PRELOADER][pmic_status] Reg[0x2BC]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21E]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21A]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21C]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x212]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x214]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x18]=0x8000 [PMIC_PRELOADER][pmic_status] Reg[0x2B6]=0x200 [PMIC_PRELOADER][pmic_status] Reg[0x2A6]=0xC6C [PMIC_PRELOADER]just_rst = 0 ignore bat check [PMIC_PRELOADER] turn off usbdl wo battery.................. [PMIC_PRELOADER][6351] is_efuse_trimed=0x1,[0xC5C]=0x8000 [PMIC_PRELOADER][6351] efuse_data[0x0]=0x21E3 [PMIC_PRELOADER][6351] efuse_data[0x1]=0x3 [PMIC_PRELOADER][6351] efuse_data[0x2]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x3]=0xBFE0 [PMIC_PRELOADER][6351] efuse_data[0x4]=0xBD54 [PMIC_PRELOADER][6351] efuse_data[0x5]=0x3FE [PMIC_PRELOADER][6351] efuse_data[0x6]=0x1620 [PMIC_PRELOADER][6351] efuse_data[0x7]=0x3C [PMIC_PRELOADER][6351] efuse_data[0x8]=0x43C [PMIC_PRELOADER][6351] efuse_data[0x9]=0x5000 [PMIC_PRELOADER][6351] efuse_data[0xA]=0x8081 [PMIC_PRELOADER][6351] efuse_data[0xB]=0x4C [PMIC_PRELOADER][6351] efuse_data[0xC]=0x9000 [PMIC_PRELOADER][6351] efuse_data[0xD]=0xC342 [PMIC_PRELOADER][6351] efuse_data[0xE]=0x2223 [PMIC_PRELOADER][6351] efuse_data[0xF]=0x9244 [PMIC_PRELOADER][6351] efuse_data[0x10]=0x36 [PMIC_PRELOADER][6351] efuse_data[0x11]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x12]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x13]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x14]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x15]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x16]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x17]=0x4 [PMIC_PRELOADER][6351] efuse_data[0x18]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x19]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1A]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1B]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1C]=0x727F [PMIC_PRELOADER][6351] efuse_data[0x1D]=0xC81E [PMIC_PRELOADER][6351] efuse_data[0x1E]=0xD6F0 [PMIC_PRELOADER][6351] efuse_data[0x1F]=0x0 [PMIC_PRELOADER][pmic_init] Reg[0x2B6]=0x201 [fan53555_hw_component_detect] exist = 1, Chip ID = 8001 [fan53555_driver_probe] fan53555_hw_init [0x0]=0x28 [0x1]=0x2C [0x2]=0x80 [0x3]=0x80 [0x4]=0x1 [0x5]=0x0 [fan53555_driver_probe] PL g_fan53555_hw_exist=1, g_fan53555_driver_ready=1 [fan53555_driver_probe] PL No I2C_EXT_BUCK_CHANNEL (7) [fan53555_driver_probe] PL No GPIO_EXT_BUCK_VSEL_PIN (0x0) [da9214_hw_component_detect] exist=1, Reg[0x105][7:4]=0xD Enable continuous high speed mode Start Enable continuous high speed mode End [da9214_driver_probe] da9214_hw_init [da9214_driver_probe] PL g_da9214_hw_exist=1, g_da9214_driver_ready=1 [da9214_driver_probe] PL No I2C_EXT_BUCK_CHANNEL (6) [da9214_driver_probe] PL No GPIO_EXT_BUCK_VSEL_PIN (0x0) ignore bat check [PMIC_PRELOADER] [pmic_init] Done...................0x04de:0xA4 vproc/vsram run as hw default [HQA]Set NV setting: Vcore = 1000 mV(0x40, should be 0x40), Vdram = 1218 mV(0x63, should be 0x63) [PLFM] Init I2C: OK(0) [PLFM] Init PWRAP: OK(0) [PLFM] Init PMIC: OK(0) [PLFM] chip_ver[0] [PTP] >> ptp_init() [PTP] >> get_devinfo() [PTP] << get_devinfo():322 [PTP] >> ptp_init_det() [PTP] PTP read VBOOT from upmu: 0x00003021 [PTP] VCORE voltage bin to 1.5V [PTP] << ptp_init_det():445 [PTP] PTP set volt: 0x00000058 [PTP] M_HW_RES0 = 0x013C8B73 [PTP] M_HW_RES1 = 0x9A5E5088 [PTP] M_HW_RES2 = 0x43A08000 [PTP] M_HW_RES3 = 0x00000000 [PTP] M_HW_RES4 = 0x00000000 [PTP] M_HW_RES5 = 0x00000000 [PTP] << ptp_init():1040 [BLDR] Build Time: 20160513-222351 [DDR Reserve] ddr reserve mode not be enabled yet ==== Dump RGU Reg ======== RGU MODE: 4D RGU LENGTH: FFE0 RGU STA: 0 RGU INTERVAL: FFF RGU SWSYSRST: 10000 RGU DEBUG_CTL: 200F1 RGU LATCH_CTL: 0 RGU DEBUG1: 0 ==== Dump RGU Reg End ==== RGU: g_rgu_satus:0 mtk_wdt_mode_config mode value=10, tmp:22000010 PL P ON WDT does not trigger reboot mtk_wdt_mode_config mode value=5D, tmp:2200005D RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(200F3), MTK_WDT_LATCH_CTL(0) WDT IRQ_EN=0x340006 WDT REQ_EN=0x3C0002 Enter mtk_kpd_gpio_set! after set KP enable: KP_SEL = 0x1C70 ! before clk_buf_enable_clkbuf4: 0x1022B100 = 0xD4C951A8 clk_buf_enable_clkbuf4: 0x1022B100 = 0x1867775 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=3967 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] rtc_boot_check1 powerkey1 = 0xEFFD, powerkey2 = 0xFEAF [RTC] bbpu = 0x2, con = 0xBB6E, osc32con = 0x5F8E, sec = 0xE7A7, yea = 0x7F74 [RTC] rtc_first_boot_init [RTC] rtc_lpd_init RTC_CON=0x486 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=3968 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] OSC32CON_ANALOG_SETTING = 0x7B00 [RTC] rtc_2sec_stat_clear [RTC] rtc_2sec_reboot_check 0x7A7 [RTC] rtc_2sec_stat_clear [RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x40, spar1 = 0x800 [RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1 [RTC] bbpu = 0x2, con = 0x486, cali = 0x7A7 [PMIC_PRELOADER] pl pmic powerkey Release [PLFM] Power key boot! [RTC] enable_dcxo first bbpu = 0x2, con = 0x486, osc32con = 0x7B00, sec = 0x7A7, yea = 0xC002 [RTC] rtc_bbpu_power_on done [RTC] rtc_enable_2sec_reboot config 0x5E7 EMI_MPUX=1 1st EMI_MPUX=0 2nd [EMI] mcp_dram_num:0,discrete_dram_num:1,enable_combo_dis:0 [Everest] ETT version 0.0.9.7 [DramcSwImpedanceCal] Start ======= K DRVP===================== 1. OCD DRVP calibration OK! DRVP=7 ======= K ODTN===================== 3. OCD ODTN calibration OK! ODTN=9 [DramcSwImpedanceCal] Done [is_pll_good] PLL 100 good [DdrPhyInit] ====Begin: Freq=400 ==== [DdrPhyInit] ====Done==== [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank1 [DdrUpdateACTiming] match AC timing 4 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 2, (u1Multi 1), Rank 1 [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=0, Rank=1 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF FF FF FF 11 FF FF FF FF 12 FF FF FF FF 13 FF FF FF FF 14 FF FF FF FF 15 FF FF FF FF 16 FF FF FF FF 17 FF FF FF FF 18 FF FF FF FF 19 FF FF FF FF 20 FF FF FF FF 21 FF FF FF FF 22 FF FF FF FF 23 FF FF FF FF 24 FF FF FF FF 25 FF FF FF FF 26 FF FF FF FF 27 FF FF FF FF 28 FF FF FF FF 29 FF FF FF FF 30 FF FF FF FF 31 FF FF FF FF 32 FF FF FF FF 33 FF FF FF FF 34 FF FF FF FF 35 FF FF FF FF 36 FF FF FF FF 37 FF FF FF FF 38 FF FF FF FF 39 FF FF FF FF 40 FF FF FF FF 41 FF FF FF FF 42 FF FF FF FF 43 FF FF FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF 54 FF FF FF FF 55 FF FF FF FF 56 FF FF FF FF 57 FF FF FF FF 58 FF FF FF FF 59 FF FF FF FF 60 FF FF FF FF 61 FF FF FF FF 62 FF FF FF FF 63 FF FF FF FF 64 FF FF FF FF 65 FF FF FF FF 66 FF FF FF FF 67 FF FF FF FF 68 FF FF FF FF 69 FF FF FF FF 70 FF FF FF FF 71 FF FF FF FF 72 FF FF FF FF 73 FF FF FF FF 74 FF FF FF FF 75 FF FF FF FF 76 FF FF FF FF 77 FF FF FF FF 78 FF FF FF FF 79 FF FF FF FF 80 FF FF FF FF 81 FF FF FF FF 82 FF FF FF FF 83 FF FF FF FF pass bytecount = 0xF0 (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 0 DQS1 delay = 0 DQS2 delay = 0 DQS3 delay = 0 DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank1 [DramcWriteLeveling] ====Done==== [DramRankNumberDetection] 1, 00000008 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming] match AC timing 4 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=400, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 1 1 0 0 0 0 1, | 1 1 1 1 1 0 0 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 1 1 1 1 32, | 0 0 0 0 1 1 1 0 33, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~31) 15, CA1 (0~31) 15, CA2 (0~31) 15, CA3 (0~31) 15, CA5 (1~32) 16, CA6 (2~32) 17, CA7 (2~32) 17, CA8 (1~31) 16, ========================================= [CA Training] Frequency=400, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 1 33, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~31) 15, CA9 (1~32) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 0 0 0 0 11 FF 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 0 0 0 0 25 0 0 0 0 26 0 0 0 0 27 0 0 0 0 28 0 FF 0 0 29 0 0 0 0 30 0 FF 0 0 31 0 0 0 0 32 0 FF 0 0 33 0 FF 0 0 34 0 FF 0 FF 35 0 FF 0 0 36 0 FF 0 FF 37 0 FF 0 FF 38 0 FF 0 FF 39 0 FF 0 FF 40 FF FF FF FF 41 FF FF FF FF 42 FF FF FF FF 43 FF FF FF FF 44 0 FF 0 FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 45 DQS1 delay = 32 DQS2 delay = 45 DQS3 delay = 36 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=400, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 1 0 |(B3->B0) 0x1211, 0x1211, 0x1010, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 2 |(B3->B0) 0x1211, 0x1211, 0x0F0F, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1111, 0x1211, 0x0B0B, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1111, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x0D0D, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 1 10 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1111 | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x1211, 0x0F0F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x1211, 0x0F0F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x1211, 0x0F0F, 0x1211, 0x0F0F | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 20 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1111 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x1211, 0x1211, 0x1313, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 3 0 |(B3->B0) 0x1211, 0x1211, 0x1817, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x1211, 0x1211, 0x1A19, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 4 |(B3->B0) 0x1313, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 3, 4) 1 3 6 |(B3->B0) 0x1313, 0x1211, 0x1F1E, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 4) Pass tap=1 1 3 8 |(B3->B0) 0x1919, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 3, 8) 1 3 10 |(B3->B0) 0x1C1C, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 12 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 3, 12) 1 3 14 |(B3->B0) 0x2323, 0x1413, 0x2323, 0x1413 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 16 |(B3->B0) 0x2323, 0x1616, 0x2323, 0x1616 | 00 00 00 00 00 00 11 11 | 0x00000000 1 3 18 |(B3->B0) 0x2323, 0x1F1F, 0x2323, 0x1F1E | 00 00 00 00 00 00 11 11 | 0x00000000 1 3 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 3, 20) [Byte 2]First pass (1, 3, 20) 1 3 22 |(B3->B0) 0x2323, 0x2221, 0x2323, 0x2120 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 3, 20) Pass tap=1 [Byte 2]Bigger pass win(1, 3, 20) Pass tap=1 1 3 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 3, 24) [Byte 2]First pass (1, 3, 24) 1 3 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 28 |(B3->B0) 0x2323, 0x2323, 0x2222, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 8) Pass tap=26 1 4 30 |(B3->B0) 0x2323, 0x2323, 0x2222, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 5 0 |(B3->B0) 0x2323, 0x2323, 0x2121, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 5 2 |(B3->B0) 0x2323, 0x2323, 0x1E1E, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 5 4 |(B3->B0) 0x2322, 0x2323, 0x1D1D, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 3, 12) Pass tap=28 1 5 6 |(B3->B0) 0x1D1C, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 8 |(B3->B0) 0x2221, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 10 |(B3->B0) 0x2221, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 12 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 14 |(B3->B0) 0x2322, 0x2121, 0x2322, 0x2121 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 3, 24) Pass tap=27 [Byte 2]Bigger pass win(1, 3, 24) Pass tap=27 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 4, 19) best DQS1 delay(2T, 0.5T, PI) = (1, 4, 2) best DQS2 delay(2T, 0.5T, PI) = (1, 4, 19) best DQS3 delay(2T, 0.5T, PI) = (1, 4, 8) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 19) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 2) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 19) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=400, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x10 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0x00000000, sum=1 15, 0x00000000, sum=2 16, 0x00000000, sum=3 17, 0x00000000, sum=4 18, 0x00000000, sum=5 pattern=5 first_step=14 total pass=6 best_step=16 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 400 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 ====DramcRxdqsGatingPostProcess (Rank = 0) ======================================== best DQS0 delay(2T, 0.5T) = (1, 0) best DQS1 delay(2T, 0.5T) = (1, 0) best DQS2 delay(2T, 0.5T) = (1, 0) best DQS3 delay(2T, 0.5T) = (1, 0) best DQS0 P1 delay(2T, 0.5T) = (1, 2) best DQS1 P1 delay(2T, 0.5T) = (1, 2) best DQS2 P1 delay(2T, 0.5T) = (1, 2) best DQS3 P1 delay(2T, 0.5T) = (1, 2) TX_dly_DQSgated check: min 2 max 2, s1ChangeDQSINCTL=-1 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=7 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=400, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 0 0 0 0 0 0 0 1 1, | 0 0 0 0 1 1 1 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 1 1 1 1 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (2~31) 16, CA1 (2~31) 16, CA2 (2~31) 16, CA3 (2~31) 16, CA5 (1~31) 16, CA6 (1~31) 16, CA7 (1~31) 16, CA8 (0~31) 15, ========================================= [CA Training] Frequency=400, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 0 1 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (1~31) 16, CA9 (0~31) 15, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF 0 FF 1 0 FF 0 0 2 0 0 0 0 3 0 FF 0 0 4 0 FF 0 0 5 0 FF 0 0 6 0 0 0 0 7 0 0 0 0 8 0 0 0 0 9 0 0 0 0 10 0 0 0 0 11 0 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 FF 0 0 0 25 FF 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 FF 0 30 FF 0 FF 0 31 FF 0 FF 0 32 FF 0 FF 0 33 FF 0 FF 0 34 FF 0 FF 0 35 FF 0 FF FF 36 FF 0 FF 0 37 FF 0 FF 0 38 FF 0 FF FF 39 FF 0 FF FF 40 FF FF FF FF 41 FF FF FF FF 42 FF FF FF FF 43 FF FF FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 24 DQS1 delay = 40 DQS2 delay = 29 DQS3 delay = 38 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=400, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 1 0 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 2 |(B3->B0) 0x1211, 0x1010, 0x1211, 0x1211 | 11 11 00 00 11 11 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x0F0E, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 10 |(B3->B0) 0x0F0F, 0x1211, 0x0F0E, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 12 |(B3->B0) 0x100F, 0x1211, 0x100F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1817 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 0 |(B3->B0) 0x1211, 0x1312, 0x1211, 0x2221 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x1211, 0x1817, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 3, 2) 1 3 4 |(B3->B0) 0x1211, 0x1D1C, 0x1312, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 3 6 |(B3->B0) 0x1212, 0x2222, 0x1413, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 3 8 |(B3->B0) 0x1413, 0x2323, 0x1514, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 2]First pass (1, 3, 8) 1 3 10 |(B3->B0) 0x2020, 0x2323, 0x2221, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 3, 12) [Byte 3]First pass (1, 3, 12) 1 3 14 |(B3->B0) 0x201F, 0x2323, 0x2221, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 12) Pass tap=1 [Byte 3]Bigger pass win(1, 3, 12) Pass tap=1 1 3 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 3, 16) [Byte 3]First pass (1, 3, 16) 1 3 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2222 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]Bigger pass win(1, 3, 2) Pass tap=27 1 4 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x201F | 00 00 00 00 00 00 11 11 | 0x00000000 1 4 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1E1D | 00 00 00 00 00 00 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1D1C | 00 00 00 00 00 00 11 11 | 0x00000000 1 5 0 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2120 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 2]Bigger pass win(1, 3, 8) Pass tap=28 1 5 2 |(B3->B0) 0x2323, 0x1D1D, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x2323, 0x1F1E, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x2323, 0x2322, 0x2222, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 16) Pass tap=27 1 5 8 |(B3->B0) 0x1C1C, 0x2322, 0x1C1C, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]Bigger pass win(1, 3, 16) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 3, 29) best DQS1 delay(2T, 0.5T, PI) = (1, 4, 11) best DQS2 delay(2T, 0.5T, PI) = (1, 4, 4) best DQS3 delay(2T, 0.5T, PI) = (1, 4, 12) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 5, 29) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 11) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 4) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 12) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=400, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x10 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0x00000000, sum=1 15, 0x00000000, sum=2 16, 0x00000000, sum=3 17, 0x00000000, sum=4 18, 0x00000000, sum=5 pattern=5 first_step=14 total pass=6 best_step=16 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 400 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=2, RANKINCTL=0, u4XRTR2R=8 [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Channel 0, Rank 0, Desity 40000000. [GetDramInforAfterCalByMRR] Channel 1, Rank 0, Desity 40000000. [EMI] MDL number = 0 DdrPhySetting_Everest_LP3()+DramcSetting_Everest_LP3() Save frequency registers setting into shuffle register. [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming] match AC timing 2 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=635, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 0 1 0 0 0 0 1, | 1 1 1 1 1 0 0 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 0 0 1 0 1 1 1 1 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~30) 15, CA1 (0~30) 15, CA2 (1~31) 16, CA3 (0~30) 15, CA5 (1~31) 16, CA6 (2~31) 16, CA7 (2~31) 16, CA8 (1~31) 16, ========================================= [CA Training] Frequency=635, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 0 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~31) 15, CA9 (2~31) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=635, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF 0 FF 0 11 FF 0 FF 0 12 FF 0 FF 0 13 FF 0 FF 0 14 FF 0 FF 0 15 FF 0 FF 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 0 0 0 0 25 0 FF 0 0 26 0 FF 0 0 27 0 FF 0 0 28 0 FF 0 0 29 0 FF 0 0 30 0 FF 0 0 31 0 FF 0 0 32 0 FF 0 0 33 0 FF 0 FF 34 0 FF 0 FF 35 0 FF 0 FF 36 0 FF 0 FF 37 0 FF 0 FF 38 0 FF 0 FF 39 0 FF 0 FF 40 0 FF 0 FF 41 0 FF 0 FF 42 0 FF 0 FF 43 0 FF 0 FF 44 0 FF FF FF 45 0 FF 0 FF 46 0 FF 0 FF 47 0 FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF 54 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 48 DQS1 delay = 25 DQS2 delay = 47 DQS3 delay = 33 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=635, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 0 7 0 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 2 |(B3->B0) 0x100F, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 4 |(B3->B0) 0x100F, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 6 |(B3->B0) 0x100F, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 14 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1111 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 16 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 18 |(B3->B0) 0x1211, 0x0D0C, 0x1211, 0x0C0C | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 20 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x0E0E | 11 11 11 11 11 11 00 00 | 0x00000000 0 7 22 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 22 |(B3->B0) 0x1211, 0x1211, 0x100F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 24 |(B3->B0) 0x1211, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 26 |(B3->B0) 0x1211, 0x1211, 0x1B1A, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 28 |(B3->B0) 0x1211, 0x1211, 0x1C1C, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 30 |(B3->B0) 0x1211, 0x1211, 0x2222, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 0 |(B3->B0) 0x1211, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 1, 0) 1 1 2 |(B3->B0) 0x1212, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1515, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1F1F, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 1, 8) 1 1 10 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 12 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x2323, 0x1212, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x2323, 0x1918, 0x2323, 0x1616 | 00 00 11 11 00 00 00 00 | 0x00000000 1 1 20 |(B3->B0) 0x2323, 0x1D1D, 0x2323, 0x1A19 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 22 |(B3->B0) 0x2323, 0x201F, 0x2323, 0x1C1C | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 1, 24) [Byte 2]First pass (1, 1, 24) 1 1 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 22 |(B3->B0) 0x2323, 0x2323, 0x2221, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 1, 0) Pass tap=27 1 2 24 |(B3->B0) 0x2323, 0x2323, 0x1B1B, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 2 26 |(B3->B0) 0x2323, 0x2323, 0x1716, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 2 28 |(B3->B0) 0x2323, 0x2323, 0x2222, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 30 |(B3->B0) 0x2322, 0x2323, 0x2020, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 1, 8) Pass tap=27 1 3 0 |(B3->B0) 0x201F, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 2 |(B3->B0) 0x1C1C, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 4 |(B3->B0) 0x1C1B, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 6 |(B3->B0) 0x2221, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 8 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 10 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 12 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 14 |(B3->B0) 0x2322, 0x2322, 0x2322, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 2]Bigger pass win(1, 1, 24) Pass tap=27 1 3 16 |(B3->B0) 0x2322, 0x1F1F, 0x2322, 0x201F | 11 11 00 00 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 1, 24) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 2, 20) best DQS1 delay(2T, 0.5T, PI) = (1, 1, 27) best DQS2 delay(2T, 0.5T, PI) = (1, 2, 19) best DQS3 delay(2T, 0.5T, PI) = (1, 2, 3) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 4, 20) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 3, 27) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 4, 19) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 4, 3) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=635, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x12 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0x00000000, sum=1 17, 0x00000000, sum=2 18, 0x00000000, sum=3 19, 0x00000000, sum=4 20, 0x00000000, sum=5 pattern=5 first_step=16 total pass=6 best_step=18 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 635 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=9 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=635, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 1 0, | 0 0 0 0 0 0 0 1 1, | 0 0 0 0 1 1 1 1 2, | 0 0 0 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 0 0 0 0 32, | 0 1 1 0 0 0 0 0 33, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (3~31) 17, CA1 (3~32) 17, CA2 (3~32) 17, CA3 (2~31) 16, CA5 (1~30) 15, CA6 (1~30) 15, CA7 (1~30) 15, CA8 (-1~30) 14, ========================================= [CA Training] Frequency=635, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 0 1 1, | 0 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 0 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (2~31) 16, CA9 (0~30) 15, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=635, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF 0 FF 1 0 FF 0 FF 2 0 FF 0 FF 3 0 FF 0 FF 4 0 FF 0 FF 5 0 FF 0 FF 6 0 FF 0 FF 7 0 FF 0 0 8 0 FF 0 0 9 0 FF 0 0 10 0 0 0 0 11 0 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 FF 0 0 0 21 FF 0 0 0 22 FF 0 0 0 23 FF 0 0 0 24 FF 0 0 0 25 FF 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 0 0 30 FF 0 FF 0 31 FF 0 FF 0 32 FF 0 FF 0 33 FF 0 FF 0 34 FF 0 FF 0 35 FF 0 FF 0 36 FF 0 FF 0 37 FF 0 FF 0 38 FF 0 FF 0 39 FF 0 FF FF 40 FF 0 FF FF 41 FF 0 FF FF 42 FF FF FF FF 43 FF 0 FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 20 DQS1 delay = 44 DQS2 delay = 30 DQS3 delay = 39 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=635, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 0 7 0 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1211 | 11 11 00 00 11 11 11 11 | 0x00000000 0 7 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 8 |(B3->B0) 0x0E0E, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 0 7 10 |(B3->B0) 0x0E0E, 0x1211, 0x0D0D, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 0 7 12 |(B3->B0) 0x100F, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 14 |(B3->B0) 0x1110, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1110 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1716 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1D1D | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 0, 24) 1 0 26 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 0 28 |(B3->B0) 0x1211, 0x1312, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 0 30 |(B3->B0) 0x1211, 0x1D1C, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 0 |(B3->B0) 0x1211, 0x2120, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 2 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 2]First pass (1, 1, 2) 1 1 4 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 6 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 8 |(B3->B0) 0x1212, 0x2323, 0x1313, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 10 |(B3->B0) 0x1918, 0x2323, 0x1D1D, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 1 1 12 |(B3->B0) 0x1E1E, 0x2323, 0x2221, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 1 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 1, 14) [Byte 3]First pass (1, 1, 14) 1 1 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 0, 24) Pass tap=27 1 2 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2121 | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1918 | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1919 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2221 | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 26 |(B3->B0) 0x2323, 0x1D1D, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 2]Bigger pass win(1, 1, 2) Pass tap=28 1 2 28 |(B3->B0) 0x2323, 0x1716, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x2323, 0x1A1A, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 0 |(B3->B0) 0x2323, 0x201F, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 4 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 6 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 8 |(B3->B0) 0x1C1B, 0x2322, 0x1A19, 0x2322 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 1, 14) Pass tap=29 [Byte 3]Bigger pass win(1, 1, 14) Pass tap=29 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 1, 19) best DQS1 delay(2T, 0.5T, PI) = (1, 2, 11) best DQS2 delay(2T, 0.5T, PI) = (1, 1, 30) best DQS3 delay(2T, 0.5T, PI) = (1, 2, 11) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 3, 19) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 4, 11) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 3, 30) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 4, 11) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=635, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x12 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFF1FFF00, sum=0 16, 0x00000000, sum=1 17, 0x00000000, sum=2 18, 0x00000000, sum=3 19, 0x00000000, sum=4 20, 0x00000000, sum=5 pattern=5 first_step=16 total pass=6 best_step=18 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 635 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=9 Save frequency registers setting into shuffle register. [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming_EMI] match AC timing 1 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=800, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 0 1 0 0 0 0 1, | 1 1 1 1 1 1 1 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 0 0 0 0 0 0 1 0 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~30) 15, CA1 (0~30) 15, CA2 (1~30) 15, CA3 (0~30) 15, CA5 (1~30) 15, CA6 (1~30) 15, CA7 (1~31) 16, CA8 (1~30) 15, ========================================= [CA Training] Frequency=800, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 0 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~30) 15, CA9 (1~31) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 LP3_JV_WORKAROUND: sepcial setting, CA delay fine-tune (15->13)n Clk Dealy is 0, CA delay is 13 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=800, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF 0 FF FF 11 FF 0 FF FF 12 FF 0 FF FF 13 FF 0 FF 0 14 FF 0 FF 0 15 FF 0 FF 0 16 FF 0 FF 0 17 FF 0 FF 0 18 FF 0 FF 0 19 FF 0 FF 0 20 FF 0 FF 0 21 FF 0 FF 0 22 FF 0 FF 0 23 FF 0 FF 0 24 FF 0 FF 0 25 FF 0 FF 0 26 FF 0 FF 0 27 FF 0 FF 0 28 FF 0 0 0 29 FF 0 FF 0 30 FF 0 FF 0 31 FF 0 0 0 32 FF FF 0 0 33 0 0 0 0 34 0 FF 0 0 35 0 FF 0 0 36 0 FF 0 0 37 0 FF 0 0 38 0 FF 0 0 39 0 FF 0 0 40 0 FF 0 0 41 0 FF 0 FF 42 0 FF 0 0 43 0 FF 0 FF 44 0 FF 0 0 45 0 FF 0 FF 46 0 FF 0 FF 47 0 FF 0 FF 48 0 FF 0 FF 49 0 FF 0 FF 50 0 FF 0 FF 51 0 FF 0 FF 52 0 FF 0 FF 53 0 FF 0 FF 54 0 FF 0 FF 55 0 FF 0 FF 56 0 FF 0 FF 57 0 FF 0 FF 58 0 FF 0 FF 59 0 FF 0 FF 60 0 FF 0 FF 61 0 FF 0 FF 62 0 FF FF FF 63 FF 0 FF FF 64 FF FF FF FF 65 FF 0 FF FF 66 FF 0 FF FF 67 FF 0 FF FF 68 FF 0 FF FF 69 FF 0 FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 63 DQS1 delay = 34 DQS2 delay = 62 DQS3 delay = 45 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=800, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 4 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 4 |(B3->B0) 0x1211, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 6 |(B3->B0) 0x1211, 0x1211, 0x0C0C, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 4 8 |(B3->B0) 0x1211, 0x1211, 0x0D0D, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 10 |(B3->B0) 0x1211, 0x1211, 0x100F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 16 |(B3->B0) 0x0F0E, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 18 |(B3->B0) 0x0D0C, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 20 |(B3->B0) 0x0B0A, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 22 |(B3->B0) 0x1010, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 4 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 2 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1111 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x1211, 0x0C0C, 0x1211, 0x0E0D | 11 11 00 00 11 11 11 11 | 0x00000000 1 5 8 |(B3->B0) 0x1211, 0x0E0E, 0x1211, 0x0D0D | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1110 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 2 |(B3->B0) 0x1211, 0x1211, 0x1111, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 4 |(B3->B0) 0x1211, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 6 |(B3->B0) 0x1211, 0x1211, 0x1312, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 8 |(B3->B0) 0x1211, 0x1211, 0x1A19, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 10 |(B3->B0) 0x1211, 0x1211, 0x2221, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 12 |(B3->B0) 0x1211, 0x1211, 0x2322, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 14 |(B3->B0) 0x1211, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 6, 14) 1 6 16 |(B3->B0) 0x1312, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 18 |(B3->B0) 0x1615, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 20 |(B3->B0) 0x1D1C, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 22 |(B3->B0) 0x2322, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 24 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 6, 24) 1 6 26 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 6 28 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 6 30 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 0 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 2 |(B3->B0) 0x2323, 0x1212, 0x2323, 0x1212 | 00 00 11 11 00 00 00 00 | 0x00000000 1 7 4 |(B3->B0) 0x2323, 0x1515, 0x2323, 0x1413 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 6 |(B3->B0) 0x2323, 0x1C1B, 0x2323, 0x1818 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 8 |(B3->B0) 0x2323, 0x2221, 0x2323, 0x1E1E | 00 00 11 11 00 00 00 00 | 0x00000000 1 7 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 7, 10) [Byte 2]First pass (1, 7, 10) 1 7 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 2 |(B3->B0) 0x2323, 0x2323, 0x2121, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 6, 14) Pass tap=26 2 0 4 |(B3->B0) 0x2323, 0x2323, 0x1E1D, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 6 |(B3->B0) 0x2323, 0x2323, 0x1616, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 8 |(B3->B0) 0x2323, 0x2323, 0x1B1B, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 10 |(B3->B0) 0x2323, 0x2323, 0x2121, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 12 |(B3->B0) 0x2323, 0x2323, 0x2322, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 14 |(B3->B0) 0x2222, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 6, 24) Pass tap=27 2 0 16 |(B3->B0) 0x1D1C, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 18 |(B3->B0) 0x1717, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 20 |(B3->B0) 0x1717, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 22 |(B3->B0) 0x1D1D, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 24 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 26 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 28 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 30 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 1 0 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 1 2 |(B3->B0) 0x2322, 0x2020, 0x2322, 0x2322 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 7, 10) Pass tap=28 [Byte 2]Bigger pass win(1, 7, 10) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (2, 0, 6) best DQS1 delay(2T, 0.5T, PI) = (1, 7, 8) best DQS2 delay(2T, 0.5T, PI) = (2, 0, 6) best DQS3 delay(2T, 0.5T, PI) = (1, 7, 19) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (2, 2, 6) best DQS1 P1 delay(2T, 0.5T, PI) = (2, 1, 8) best DQS2 P1 delay(2T, 0.5T, PI) = (2, 2, 6) best DQS3 P1 delay(2T, 0.5T, PI) = (2, 1, 19) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=800, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x13 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0xFFFFFFFF, sum=0 17, 0x00000040, sum=0 18, 0x00000000, sum=1 19, 0x00000000, sum=2 20, 0x00000000, sum=3 21, 0x00000000, sum=4 22, 0x00000000, sum=5 pattern=5 first_step=18 total pass=6 best_step=20 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 800 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3 TX_dly_DQSgated check: min 3 max 4, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=10 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=800, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 1 0, | 0 0 0 0 1 1 1 1 1, | 0 0 0 1 1 1 1 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 0 1 0 31, | 1 1 1 0 0 0 0 0 32, | 0 1 0 0 0 0 0 0 33, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (2~31) 16, CA1 (2~32) 17, CA2 (2~31) 16, CA3 (1~30) 15, CA5 (0~30) 15, CA6 (0~29) 14, CA7 (0~30) 15, CA8 (-1~29) 14, ========================================= [CA Training] Frequency=800, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 1 0, | 0 1 1, | 0 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 0 31, | 1 0 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (2~31) 16, CA9 (-1~29) 14, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 LP3_JV_WORKAROUND: sepcial setting, CA delay fine-tune (15->13)n Clk Dealy is 0, CA delay is 13 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=800, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF FF FF 1 0 FF FF FF 2 0 FF FF FF 3 0 FF FF FF 4 0 FF FF FF 5 0 FF FF FF 6 0 FF 0 FF 7 0 FF 0 FF 8 0 FF 0 FF 9 0 FF 0 FF 10 0 FF 0 FF 11 0 FF 0 FF 12 0 FF 0 FF 13 0 FF 0 FF 14 0 FF 0 FF 15 0 FF 0 FF 16 0 FF 0 FF 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 FF 0 0 0 25 FF 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 0 0 30 FF 0 0 0 31 FF 0 0 0 32 FF 0 0 0 33 FF 0 0 0 34 FF 0 0 0 35 FF 0 0 0 36 FF 0 FF 0 37 FF 0 FF 0 38 FF 0 FF 0 39 FF 0 FF 0 40 FF 0 FF 0 41 FF 0 FF 0 42 FF 0 FF 0 43 FF 0 FF 0 44 FF 0 FF 0 45 FF 0 FF 0 46 FF 0 FF 0 47 FF 0 FF 0 48 FF 0 FF FF 49 FF FF FF FF 50 FF 0 FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF 54 FF FF FF FF 55 FF FF FF FF 56 0 FF FF FF 57 0 FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 24 DQS1 delay = 51 DQS2 delay = 36 DQS3 delay = 48 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=800, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 4 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1010 | 11 11 11 11 11 11 00 00 | 0x00000000 1 4 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1111 | 11 11 11 11 11 11 00 00 | 0x00000000 1 4 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 6 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 8 |(B3->B0) 0x1211, 0x0C0C, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 10 |(B3->B0) 0x1211, 0x0B0A, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 12 |(B3->B0) 0x1211, 0x0E0E, 0x1211, 0x1211 | 11 11 00 00 11 11 11 11 | 0x00000000 1 4 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 20 |(B3->B0) 0x1111, 0x1211, 0x0F0F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 22 |(B3->B0) 0x1111, 0x1211, 0x1010, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 24 |(B3->B0) 0x0C0B, 0x1211, 0x0B0A, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 26 |(B3->B0) 0x1010, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 28 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 00 00 | 0x00000000 1 5 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1616 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1B1B | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2222 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 6, 4) 1 6 6 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 8 |(B3->B0) 0x1211, 0x1312, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 10 |(B3->B0) 0x1211, 0x1C1B, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 12 |(B3->B0) 0x1211, 0x1E1D, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 14 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 2]First pass (1, 6, 14) 1 6 16 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 18 |(B3->B0) 0x1211, 0x2323, 0x1111, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 20 |(B3->B0) 0x1211, 0x2323, 0x1212, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 1 6 22 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 24 |(B3->B0) 0x1615, 0x2323, 0x1818, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 26 |(B3->B0) 0x1E1E, 0x2323, 0x2120, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 6, 28) [Byte 3]First pass (1, 6, 28) 1 6 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2221 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 6, 4) Pass tap=28 1 7 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1A19 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x201F | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 6 |(B3->B0) 0x2323, 0x2121, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 2]Bigger pass win(1, 6, 14) Pass tap=28 2 0 8 |(B3->B0) 0x2323, 0x1413, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 10 |(B3->B0) 0x2323, 0x1919, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 12 |(B3->B0) 0x2323, 0x1D1C, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 14 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 16 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 18 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 20 |(B3->B0) 0x2020, 0x2322, 0x1C1B, 0x2322 | 00 00 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 6, 28) Pass tap=28 [Byte 3]Bigger pass win(1, 6, 28) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 7, 0) best DQS1 delay(2T, 0.5T, PI) = (1, 7, 24) best DQS2 delay(2T, 0.5T, PI) = (1, 7, 10) best DQS3 delay(2T, 0.5T, PI) = (1, 7, 24) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (2, 1, 0) best DQS1 P1 delay(2T, 0.5T, PI) = (2, 1, 24) best DQS2 P1 delay(2T, 0.5T, PI) = (2, 1, 10) best DQS3 P1 delay(2T, 0.5T, PI) = (2, 1, 24) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=800, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x13 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0xFFFFFFFF, sum=0 17, 0x00000000, sum=1 18, 0x00000000, sum=2 19, 0x00000000, sum=3 20, 0x00000000, sum=4 21, 0x00000000, sum=5 pattern=5 first_step=17 total pass=6 best_step=19 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 800 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3 TX_dly_DQSgated check: min 3 max 4, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=10 [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [LJ_PHYPLL_0] waiting for K_Band [LJ_PHYPLL_0], PASS=1, FAIL=0, BAND=19 [LJ_PHYPLL_1] waiting for K_Band [LJ_PHYPLL_1], PASS=1, FAIL=0, BAND=1A [LJ_PHYPLL_2] waiting for K_Band [LJ_PHYPLL_2], PASS=1, FAIL=0, BAND=1B [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank0 [DramcDFS] Before DVFS, disable FB_CK divide [DramcDFS] Before DVFS, disable M_CK free-run divider [DramcDFS] DVFS to type(1270) flow start DramcDFSDirectJump(shuffle start) DMA = 0 DramcDFSDirectJump(leave shuffle) DMA = 0 [DramcDFS] DVFS end [DramcDFS] After DLL lock, enable FB_CK divider End [DramcDFS] After DVFS enable M_CK free-run div EMI_CONA=20102017 EMI_CONH=0 ============================================= EMI offset:0, value:20102017 EMI offset:4, value:0 EMI offset:8, value:17283544 EMI offset:C, value:0 EMI offset:10, value:A1A0B1A EMI offset:14, value:0 EMI offset:18, value:3657587A EMI offset:1C, value:0 EMI offset:20, value:FFFF0848 EMI offset:24, value:0 EMI offset:28, value:4210000 EMI offset:2C, value:0 EMI offset:30, value:2B2B2A38 EMI offset:34, value:0 EMI offset:38, value:0 EMI offset:3C, value:0 EMI offset:40, value:8813 EMI offset:44, value:0 EMI offset:48, value:FFFF1FED EMI offset:4C, value:0 EMI offset:50, value:0 EMI offset:54, value:0 EMI offset:58, value:0 EMI offset:5C, value:0 EMI offset:60, value:63C EMI offset:64, value:0 EMI offset:68, value:0 EMI offset:6C, value:0 EMI offset:70, value:0 EMI offset:74, value:0 EMI offset:78, value:889A0C3F EMI offset:7C, value:0 EMI offset:80, value:0 EMI offset:84, value:0 EMI offset:88, value:0 EMI offset:8C, value:0 EMI offset:90, value:0 EMI offset:94, value:0 EMI offset:98, value:0 EMI offset:9C, value:0 EMI offset:A0, value:0 EMI offset:A4, value:0 EMI offset:A8, value:0 EMI offset:AC, value:0 EMI offset:B0, value:0 EMI offset:B4, value:0 EMI offset:B8, value:0 EMI offset:BC, value:0 EMI offset:C0, value:0 EMI offset:C4, value:0 EMI offset:C8, value:0 EMI offset:CC, value:0 EMI offset:D0, value:CFCFCFCF EMI offset:D4, value:0 EMI offset:D8, value:CFCFCFCF EMI offset:DC, value:0 EMI offset:E0, value:33433343 EMI offset:E4, value:0 EMI offset:E8, value:62027 EMI offset:EC, value:0 EMI offset:F0, value:38460000 EMI offset:F4, value:0 EMI offset:F8, value:0 EMI offset:FC, value:0 EMI offset:100, value:7F807048 EMI offset:104, value:0 EMI offset:108, value:7F807F40 EMI offset:10C, value:0 EMI offset:110, value:A0A070D7 EMI offset:114, value:0 EMI offset:118, value:70C5 EMI offset:11C, value:0 EMI offset:120, value:40306045 EMI offset:124, value:0 EMI offset:128, value:A0A070D8 EMI offset:12C, value:0 EMI offset:130, value:A0A07042 EMI offset:134, value:4000 EMI offset:138, value:2010704D EMI offset:13C, value:0 EMI offset:140, value:20407188 EMI offset:144, value:20406188 EMI offset:148, value:9719595E EMI offset:14C, value:9719595E EMI offset:150, value:64F3FC79 EMI offset:154, value:64F3FC79 EMI offset:158, value:FF01FF00 EMI offset:15C, value:0 Settings after calibration ... === [DramcRunTimeConfig] === HW_GATING: ON DFS_HW_SYNC_GATING_TRACKING: OFF ZQCS_ENABLE: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON SPM_CONTROL_AFTERK: ON TEMP_SENSOR_ENABLE: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x46000000) 0:dram_rank_size:80000000 dram_rank_size[0] = 0x80000000 dram_rank_size[1] = 0x0 dram_rank_size[2] = 0x0 dram_rank_size[3] = 0x0 RGU rgu_dram_reserved:MTK_WDT_MODE(2200005D) [Dram_Buffer] dram_buf_t size: 0x9C280 [Dram_Buffer] part_hdr_t size: 0x200 [Dram_Buffer] sizeof(boot_arg_t): 0xD00 [Dram_Buffer] g_dram_buf start addr: 0x44800000 [Dram_Buffer] g_dram_buf->msdc_gpd_pool start addr: 0x4489C1C0 [Dram_Buffer] g_dram_buf->msdc_bd_pool start addr: 0x4489C200 RAM_CONSOLE using default RAM_CONSOLE start: 0x12D000, size: 0xC00, sig: 0x7F9D7D24 RAM_CONSOLE wdt status (0x0)=0x0 [msdc_init]: msdc0 Host controller intialization start [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [msdc_init]: msdc0 Host controller intialization done [SD0] Switch to High-Speed mode! [SD0] Switch to SDR buswidth [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [SD0] Switch to High-Speed mode! [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0) [mmc_init_card]: finish successfully [PLFM] Init Boot Device: OK(0) 0:dram_rank_size:80000000 0:dram_rank_size:80000000 orig_dram_info[0] start: 0x0000000040000000, size: 0x0000000080000000 [Enable 4GB Support] 4GB_flag 0x0 total_dram_size: 0x0000000080000000, max_dram_size: 0xFFFFFFFFFFFFFFFF [GPT_PL]Parsing Primary GPT now... [GPT_PL][0]name=recovery, part_id=8, start_sect=0x40, nr_sects=0x8000 [GPT_PL][1]name=para, part_id=8, start_sect=0x8040, nr_sects=0x400 [GPT_PL][2]name=expdb, part_id=8, start_sect=0x8440, nr_sects=0x5000 [GPT_PL][3]name=frp, part_id=8, start_sect=0xD440, nr_sects=0x800 [GPT_PL][4]name=nvcfg, part_id=8, start_sect=0xDC40, nr_sects=0x4000 [GPT_PL][5]name=nvdata, part_id=8, start_sect=0x11C40, nr_sects=0x10000 [GPT_PL][6]name=metadata, part_id=8, start_sect=0x21C40, nr_sects=0x10000 [GPT_PL][7]name=protect1, part_id=8, start_sect=0x31C40, nr_sects=0x4000 [GPT_PL][8]name=protect2, part_id=8, start_sect=0x35C40, nr_sects=0x63C0 [GPT_PL][9]name=seccfg, part_id=8, start_sect=0x3C000, nr_sects=0x4000 [GPT_PL][10]name=oemkeystore, part_id=8, start_sect=0x40000, nr_sects=0x1000 [GPT_PL][11]name=proinfo, part_id=8, start_sect=0x41000, nr_sects=0x1800 [GPT_PL][12]name=md1img, part_id=8, start_sect=0x42800, nr_sects=0xC000 [GPT_PL][13]name=md1dsp, part_id=8, start_sect=0x4E800, nr_sects=0x2000 [GPT_PL][14]name=md1arm7, part_id=8, start_sect=0x50800, nr_sects=0x1800 [GPT_PL][15]name=md3img, part_id=8, start_sect=0x52000, nr_sects=0x2800 [GPT_PL][16]name=scp1, part_id=8, start_sect=0x54800, nr_sects=0x800 [GPT_PL][17]name=scp2, part_id=8, start_sect=0x55000, nr_sects=0x800 [GPT_PL][18]name=nvram, part_id=8, start_sect=0x55800, nr_sects=0x2800 [GPT_PL][19]name=lk, part_id=8, start_sect=0x58000, nr_sects=0x400 [GPT_PL][20]name=lk2, part_id=8, start_sect=0x58400, nr_sects=0x400 [GPT_PL][21]name=boot, part_id=8, start_sect=0x58800, nr_sects=0x8000 [GPT_PL][22]name=logo, part_id=8, start_sect=0x60800, nr_sects=0x4000 [GPT_PL][23]name=tee1, part_id=8, start_sect=0x64800, nr_sects=0x2800 [GPT_PL][24]name=tee2, part_id=8, start_sect=0x67000, nr_sects=0x2800 [GPT_PL][25]name=keystore, part_id=8, start_sect=0x69800, nr_sects=0x6800 [GPT_PL][26]name=system, part_id=8, start_sect=0x70000, nr_sects=0x500000 [GPT_PL][27]name=cache, part_id=8, start_sect=0x570000, nr_sects=0xD8000 [GPT_PL][28]name=userdata, part_id=8, start_sect=0x648000, nr_sects=0x83FFDF [GPT_PL][29]name=flashinfo, part_id=8, start_sect=0xE87FDF, nr_sects=0x8000 [GPT_PL]Success to find valid GPT. LOG_STORE:sram->sig value 0xB937ACD0! LOG_STORE:sram buff header is not match, format all! LOG_STORE:log_to_emmc function flag 0x0! LOG_STORE:sram_dram_buff->sig error 0x0! mblock[0].start: 0x0000000040000000, sz: 0x0000000080000000, limit: 0x00000000C0000000, max_addr: 0x0000000000000000, max_rank: 0, target: -1, mblock[].rank: 0, reserved_addr: 0x00000000BFFE0000,reserved_size: 0x0000000000020000 mblock_reserve dbg[0]: 0, 1, 1, 1, 1 mblock_reserve: 00000000BFFE0000 - 00000000C0000000 from mblock 0 mblock-debug[0].start: 0x0000000040000000, sz: 0x000000007FFE0000 LOG_STORE:sram_header 0x12DC00,sig 0xABCD1234, sram_dram_buff 0x12DC18, buf_addr 0xBFFE0000, pl_buff_header 0xBFFE0000! [PART] blksz: 512B [PART] [0x0000000000008000-0x0000000001007FFF] "recovery" (32768 blocks) [PART] [0x0000000001008000-0x0000000001087FFF] "para" (1024 blocks) [PART] [0x0000000001088000-0x0000000001A87FFF] "expdb" (20480 blocks) [PART] [0x0000000001A88000-0x0000000001B87FFF] "frp" (2048 blocks) [PART] [0x0000000001B88000-0x0000000002387FFF] "nvcfg" (16384 blocks) [PART] [0x0000000002388000-0x0000000004387FFF] "nvdata" (65536 blocks) [PART] [0x0000000004388000-0x0000000006387FFF] "metadata" (65536 blocks) [PART] [0x0000000006388000-0x0000000006B87FFF] "protect1" (16384 blocks) [PART] [0x0000000006B88000-0x00000000077FFFFF] "protect2" (25536 blocks) [PART] [0x0000000007800000-0x0000000007FFFFFF] "seccfg" (16384 blocks) [PART] [0x0000000008000000-0x00000000081FFFFF] "oemkeystore" (4096 blocks) [PART] [0x0000000008200000-0x00000000084FFFFF] "proinfo" (6144 blocks) [PART] [0x0000000008500000-0x0000000009CFFFFF] "md1img" (49152 blocks) [PART] [0x0000000009D00000-0x000000000A0FFFFF] "md1dsp" (8192 blocks) [PART] [0x000000000A100000-0x000000000A3FFFFF] "md1arm7" (6144 blocks) [PART] [0x000000000A400000-0x000000000A8FFFFF] "md3img" (10240 blocks) [PART] [0x000000000A900000-0x000000000A9FFFFF] "scp1" (2048 blocks) [PART] [0x000000000AA00000-0x000000000AAFFFFF] "scp2" (2048 blocks) [PART] [0x000000000AB00000-0x000000000AFFFFFF] "nvram" (10240 blocks) [PART] [0x000000000B000000-0x000000000B07FFFF] "lk" (1024 blocks) [PART] [0x000000000B080000-0x000000000B0FFFFF] "lk2" (1024 blocks) [PART] [0x000000000B100000-0x000000000C0FFFFF] "boot" (32768 blocks) [PART] [0x000000000C100000-0x000000000C8FFFFF] "logo" (16384 blocks) [PART] [0x000000000C900000-0x000000000CDFFFFF] "tee1" (10240 blocks) [PART] [0x000000000CE00000-0x000000000D2FFFFF] "tee2" (10240 blocks) [PART] [0x000000000D300000-0x000000000DFFFFFF] "keystore" (26624 blocks) [PART] [0x000000000E000000-0x00000000ADFFFFFF] "system" (5242880 blocks) [PART] [0x00000000AE000000-0x00000000C8FFFFFF] "cache" (884736 blocks) [PART] [0x00000000C9000000-0x00000001D0FFBDFF] "userdata" (8650719 blocks) [PART] [0x00000001D0FFBE00-0x00000001D1FFBDFF] "flashinfo" (32768 blocks) €€€€€€€€€€€[BLDR] Tool connection is unlocked platform_vusb_on VUSB33 is on platform_vusb_on VA10 is on platform_vusb_on VA10 select to 0.95V step A2 : Standard USB Host! [PLFM] USB cable in [TOOL] USB enum timeout (Yes), handshake timeout(Yes) [TOOL] Enumeration(Start) HS is detected HS is detected [TOOL] Enumeration(End): OK 374ms [TOOL] 0xa0 sync time 480ms [UDL] part: lk, addr: 0x45FFFE00, size: 0x900000 [UDL] part: logo, addr: 0x4E8FFE00, size: 0x600000 [UDL] part: boot, addr: 0x40080000, size: 0x4000000 [UDL] part: tee1, addr: 0x1003C0, size: 0x40000 [UDL] SEND_IMAGE: img_name = lk [UDL] SEND_IMAGE: img_len = 0x6CEE0 [UDL] SEND_IMAGE: Verify PASS. [UDL] SEND_IMAGE: img_addr = 0x45FFFE00 [UDL] SEND_IMAGE: My Checksum = 0x944D3977 [UDL] SEND_IMAGE: XFLASH checksum = 0x944D3977 [UDL] SEND_IMAGE: img_name = logo [UDL] SEND_IMAGE: img_len = 0x17BCD0 [UDL] SEND_IMAGE: Verify PASS. [UDL] SEND_IMAGE: img_addr = 0x4E8FFE00 [UDL] SEND_IMAGE: My Checksum = 0xAB9206A7 [UDL] SEND_IMAGE: XFLASH checksum = 0xAB9206A7 [UDL] SEND_IMAGE: img_name = tee1 [UDL] SEND_IMAGE: img_len = 0x14000 [UDL] SEND_IMAGE: Verify PASS. [UDL] SEND_IMAGE: img_addr = 0x1003C0 [UDL] SEND_IMAGE: My Checksum = 0xCE2B03BA [UDL] SEND_IMAGE: XFLASH checksum = 0xCE2B03BA [UDL] BOOT_IMAGE: tee1 (B)tz_dapc_sec_init is 0x4 (E)tz_dapc_sec_init is 0x4 (E)MAS0=0x0 (E)MAS1=0x0 mblock[0].start: 0x0000000040000000, sz: 0x000000007FFE0000, limit: 0x00000000C0000000, max_addr: 0x0000000000000000, max_rank: 0, target: -1, mblock[].rank: 0, reserved_addr: 0x00000000BFFA0000,reserved_size: 0x0000000000040000 mblock_reserve dbg[0]: 0, 1, 1, 1, 1 mblock_reserve: 00000000BFFA0000 - 00000000BFFE0000 from mblock 0 mblock-debug[0].start: 0x0000000040000000, sz: 0x000000007FFA0000 [PLFM] boot to LK by ATAG. [xxxx1][preloader]first_volt = 0x68 [xxxx1][preloader]second_volt = 0x58 [xxxx1][preloader]third_volt = 0x48 [xxxx1][preloader]have_550 = 0x0 BOOT_REASON: 0 BOOT_MODE: 99 META_COM TYPE: 0 META_COM ID: 0 META_COM PORT: 285220864 LOG_COM PORT: 285220864 LOG_COM BAUD: 921600 LOG_COM EN: 1 MEM_NUM: 1 MEM_SIZE: 0x7FFA0000 mblock num: 0x1 mblock start: 0x0000000040000000 mblock size: 0x000000007FFA0000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 orig_dram num: 0x1 orig_dram start: 0x0000000040000000 orig_dram size: 0x0000000080000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 lca start: 0x0000000000000000 lca size: 0x0000000000000000 tee start: 0x00000000BFFA0000 tee size: 0x0000000000040000 MD_INFO: 0x0 MD_INFO: 0x0 MD_INFO: 0x0 MD_INFO: 0x0 BOOT_TIME: 4984 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 SEC_INFO: 0x0 SEC_INFO: 0x0 PART_NUM: 0 PART_INFO: 0x44879A84 EFLAG: 0 DDR_RESERVE: 0 DDR_RESERVE: 0 DRAM_BUF: 639616 SRAM start: 0x12A000 SRAM size: 0x6000 [TZ_INIT] atf_log_port : 0x11002000 [TZ_INIT] atf_log_baudrate : 0xE1000 [TZ_INIT] atf_irq_num : 325 [TZ_INIT] ATF log buffer start : 0xBFFA0000 [TZ_INIT] ATF log buffer size : 0x40000 [TZ_INIT] ATF aee buffer start : 0xBFFDC000 [TZ_INIT] ATF aee buffer size : 0x4000 [UDL] Jump to ATF [BLDR] jump to 0x46000000 [BLDR] <0x46000000>=0xEA000007 [BLDR] <0x46000004>=0xEA009417 [TZ_SEC_CFG] SRAMROM Secure Addr 0x2A000 [TZ_SEC_CFG] SRAMROM Secure Control 0x40000000 [TZ_SEC_CFG] SRAMROM Secure Control 0x40000B69 [TZ_SEC_CFG] SRAMROM Secure Control 0x51680B69 [TZ_INIT] ATF entry addr, dram addr: 0x101000, 0x44600000 [TZ_EMI_MPU] MPU [0x44600000-0x4460FFFF] [TZ_INIT] set secure memory protection : 0x44600000, 0x4460FFFF (1) [TZ_INIT] Jump to ATF, then 0x46000000 [ATF](0)[0.7]CPUxGPT reg(201) [ATF](0)[0.327]BL33 boot argument location=0x4489c240 [ATF](0)[0.964]BL33 boot argument size=0xd00 [ATF](0)[0.1485]BL33 start addr=0x46000000 [ATF](0)[0.1984]teearg addr=0x100000 [ATF](0)[0.2413]atf_magic=0x4d415446 [ATF](0)[0.2842]tee_support=0x0 [ATF](0)[0.3212]tee_entry=0x0 [ATF](0)[0.3559]tee_boot_arg_addr=0x100100 [ATF](0)[0.4057]atf_log_port=0x11002000 [ATF](0)[0.4521]atf_log_baudrate=0xe1000 [ATF](0)[0.4996]atf_log_buf_start=0xbffa0000 [ATF](0)[0.5518]atf_log_buf_size=0x40000 [ATF](0)[0.5993]atf_aee_debug_buf_start=0xbffdc000 [ATF](0)[0.6584]atf_aee_debug_buf_size=0x4000 [ATF](0)[0.7116]atf_irq_num=325 [ATF](0)[0.7487]BL33_START_ADDRESS=0x46000000 [ATF](0)[0.8020]atf chip_code[279] [ATF](0)[0.8403]atf chip_ver[0] [ATF](0)[0.8770]###@@@ MP0_MISC_CONFIG3:0x000f0000 @@@### [ATF](0)[0.9424]###@@@ MP0_MISC_CONFIG3:0x000fe000 @@@### [ATF](0)[0.10085]mmap atf buffer : 0xbffa0000, 0x40000 [ATF](0)[0.10847]mmap atf buffer (force 2MB aligned): 0xbfe00000, 0x200000 [ATF](0)[0.11708]###@@@ CPUSYS1 OFF @@@### [ATF](0)[0.12180]power_off_little_cl cl:1 [ATF](0)[0.12665]INFRA_TOPAXI_PROTECTEN1 (0x10001234):0x00000222 [ATF](0)[0.13421]end NOTICE: BL3-1: v1.0(debug):3eddbd5 NOTICE: BL3-1: Built : 18:23:41, Jun 7 2016 [ATF](0)[0.16429]crash flag: 0xffffffff [ATF](0)[0.16870]sta=0x0 int=0xffc [ATF](0)[0.17268]is_power_on_boot: true [ATF](0)[0.20632]mt_log_setup - atf_buf_addr : 0xbffa0100 [ATF](0)[0.21238]mt_log_setup - atf_buf_size : 0x29f00 [ATF](0)[0.21841]mt_log_setup - atf_write_pos : 0xbffa0100 [ATF](0)[0.22487]mt_log_setup - atf_read_pos : 0xbffa0100 [ATF](0)[0.23123]mt_log_setup - atf_buf_lock : 0x0 [ATF](0)[0.23682]mt_log_setup - mt_log_buf_end : 0xbffc9fff [ATF](0)[0.24339]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000 [ATF](0)[0.25050]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000 [ATF](0)[0.25804]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0xa000 [ATF](0)[0.26472]mt_log_setup - PLATFORM_CORE_COUNT : 0xa [ATF](0)[0.27107]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x0(Hi), 0xbffd2000(Low) [ATF](0)[0.28087]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x0(Hi), 0xbffd3000(Low) [ATF](0)[0.29067]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x0(Hi), 0xbffd4000(Low) [ATF](0)[0.30047]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x0(Hi), 0xbffd5000(Low) [ATF](0)[0.31027]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x0(Hi), 0xbffd6000(Low) [ATF](0)[0.32007]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x0(Hi), 0xbffd7000(Low) [ATF](0)[0.32987]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x0(Hi), 0xbffd8000(Low) [ATF](0)[0.33967]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x0(Hi), 0xbffd9000(Low) [ATF](0)[0.34947]mt_log_setup - atf_except_write_pos_per_cpu[8]: 0x0(Hi), 0xbffda000(Low) [ATF](0)[0.35927]mt_log_setup - atf_except_write_pos_per_cpu[9]: 0x0(Hi), 0xbffdb000(Low) [ATF](0)[0.36907]mt_log_setup - atf_crash_flag : 0x41544641 [ATF](0)[0.37564]mt_log_setup - atf_crash_log_addr : 0x0 [ATF](0)[0.38189]mt_log_setup - atf_crash_log_size : 0x0 [ATF](0)[0.38814]ATF log service is registered (0xbffa0000, aee:0xbffdc000) [ATF](0)[0.39643]BL3-1: v1.0(debug):3eddbd5 [ATF](0)[0.40128]BL3-1: Built : 18:23:41, Jun 7 2016 INFO: BL3-1: Initializing runtime services [ATF](0)[0.41297][BL31] Jump to FIQD for initialization! INFO: BL3-1: Preparing for EL3 exit to normal world, LK INFO: BL3-1: Next image address = 0x46000000 INFO: BL3-1: Next image spsr = 0x1d3 [ATF](0)[0.43523][BL31] Final dump! [LOG_STORE:log_store_init. LOG_STORE:sram buff header 0x12dc00,buff address 0xbffe0000, sig 0xcdab3412, buff_size 0x20000, pl 0x685b : 0x28, lk size0x0 : 0x28! LOG_STORE:value S. LOG_STORE: buff ready. 0] [PWRAP] pwrap_init_lk [0] [PWRAP] is_pwrap_init_done 1 [0] [BATTERY] /QON counter still counting... [10] platform_init() [20] [msdc_init]: msdc0 Host controller intialization start [20] [info][msdc_set_startbit 489] read data start bit at rising edge [20] [info][msdc_config_clksrc] input clock is 400000kHz [20] [SD0] Bus Width: 1 [20] [info][msdc_config_clksrc] input clock is 400000kHz [20] [info][msdc_set_startbit 489] read data start bit at rising edge [20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [20] [msdc_init]: msdc0 Host controller intialization done [20] [mmc_init]: msdc0 start mmc_init_card() [20] [mmc_init_card]: start [120] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 4MB, csd.write_prot_grpsz = 7,csd.erase_sctsz = 1024 [120] [mmc_decode_ext_csd]: mmc_set_wp_size 4MB [120] [SD0] Switch to High-Speed mode! [120] [SD0] Switch to SDR buswidth [120] [info][msdc_config_clksrc] input clock is 400000kHz [120] [info][msdc_set_startbit 489] read data start bit at rising edge [140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [140] [SD0] Bus Width: 8 [140] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0) [140] [mmc_init_mem_card 3543][SD0] Initialized, eMMC50 [140] before host->cur_bus_clk(259740) [140] [SD0] Switch to High-Speed mode! [140] [info][msdc_config_clksrc] input clock is 400000kHz [140] [info][msdc_set_startbit 489] read data start bit at rising edge [140] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0) [140] host->cur_bus_clk(50000000) [140] [mmc_init_card]: finish successfully [160] [mt_part_register_device] [160] [GPT_LK]Parsing Primary GPT now... [160] [GPT_LK][0]name=recovery, part_id=8, start_sect=0x40, nr_sects=0x8000 [160] [GPT_LK][1]name=para, part_id=8, start_sect=0x8040, nr_sects=0x400 [160] [GPT_LK][2]name=expdb, part_id=8, start_sect=0x8440, nr_sects=0x5000 [160] [GPT_LK][3]name=frp, part_id=8, start_sect=0xd440, nr_sects=0x800 [160] [GPT_LK][4]name=nvcfg, part_id=8, start_sect=0xdc40, nr_sects=0x4000 [160] [GPT_LK][5]name=nvdata, part_id=8, start_sect=0x11c40, nr_sects=0x10000 [160] [GPT_LK][6]name=metadata, part_id=8, start_sect=0x21c40, nr_sects=0x10000 [180] [GPT_LK][7]name=protect1, part_id=8, start_sect=0x31c40, nr_sects=0x4000 [180] [GPT_LK][8]name=protect2, part_id=8, start_sect=0x35c40, nr_sects=0x63c0 [180] [GPT_LK][9]name=seccfg, part_id=8, start_sect=0x3c000, nr_sects=0x4000 [180] [GPT_LK][10]name=oemkeystore, part_id=8, start_sect=0x40000, nr_sects=0x1000 [180] [GPT_LK][11]name=proinfo, part_id=8, start_sect=0x41000, nr_sects=0x1800 [180] [GPT_LK][12]name=md1img, part_id=8, start_sect=0x42800, nr_sects=0xc000 [180] [GPT_LK][13]name=md1dsp, part_id=8, start_sect=0x4e800, nr_sects=0x2000 [180] [GPT_LK][14]name=md1arm7, part_id=8, start_sect=0x50800, nr_sects=0x1800 [180] [GPT_LK][15]name=md3img, part_id=8, start_sect=0x52000, nr_sects=0x2800 [180] [GPT_LK][16]name=scp1, part_id=8, start_sect=0x54800, nr_sects=0x800 [180] [GPT_LK][17]name=scp2, part_id=8, start_sect=0x55000, nr_sects=0x800 [200] [GPT_LK][18]name=nvram, part_id=8, start_sect=0x55800, nr_sects=0x2800 [200] [GPT_LK][19]name=lk, part_id=8, start_sect=0x58000, nr_sects=0x400 [200] [GPT_LK][20]name=lk2, part_id=8, start_sect=0x58400, nr_sects=0x400 [200] [GPT_LK][21]name=boot, part_id=8, start_sect=0x58800, nr_sects=0x8000 [200] [GPT_LK][22]name=logo, part_id=8, start_sect=0x60800, nr_sects=0x4000 [200] [GPT_LK][23]name=tee1, part_id=8, start_sect=0x64800, nr_sects=0x2800 [200] [GPT_LK][24]name=tee2, part_id=8, start_sect=0x67000, nr_sects=0x2800 [200] [GPT_LK][25]name=keystore, part_id=8, start_sect=0x69800, nr_sects=0x6800 [200] [GPT_LK][26]name=system, part_id=8, start_sect=0x70000, nr_sects=0x500000 [200] [GPT_LK][27]name=cache, part_id=8, start_sect=0x570000, nr_sects=0xd8000 [200] [GPT_LK][28]name=userdata, part_id=8, start_sect=0x648000, nr_sects=0x83ffdf [200] [GPT_LK][29]name=flashinfo, part_id=8, start_sect=0xe87fdf, nr_sects=0x8000 [220] [GPT_LK]Success to find valid GPT. [220] [SD0] boot device found [220] [PART_LK][get_part] para [220] [LK_BOOT] Load 'para' partition to 0x46087344 (6144 bytes in 2 ms) [220] [PART_LK][get_part] boot [220] [LK_BOOT] Load 'boot' partition to 0x46900000 (608 bytes in 3 ms) [220] Warning! No bootopt info! [220] [PART_LK][get_part] boot [400] [LK_BOOT] Load 'boot' partition to 0x46900000 (3688448 bytes in 84 ms) €€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€Set SRAM to 1.1V... Read SRAM1 = 0xB0B0B0B... Read SRAM2 = 0xB0B0B0B... Read SRAM2 CTRL6= 0x88888888... Pll init start... mtcmos Start.. mtcmos Done! Pll init Done! USB PRB0 LineState: 0 [U] USB cable/ No Cable inserted! [PLFM] Keep stay in USB Mode [PWRAP] pwrap_init_preloader [PWRAP] Preloader pwrap_init start!!!!!!!!!!!!! [PWRAP] Dump PD_CFG0=0x0 ([10]=MI,[11]=MO, [12]=CK, [13]=CSN), [PWRAP] Dump PU_CFG0=0x0 ([10]=MI,[11]=MO, [12]=CK, [13]=CSN), [PWRAP] SMT setting is OK.[PWRAP] DRV setting is OK.[PWRAP] slave IO setting is OK.[PWRAP] start reset wrapper [PWRAP] pwrap_init---- reset ok [PWRAP] spi clk set .... [PWRAP] pwrap_init---- clk set ok [PWRAP] pwrap_init---- dcm enable [PWRAP] pwrap_init---- slave reset ok [PWRAP] pwrap_init---- wacs2 enable ok [PWRAP] pwrap_init---- debug: init_reg_clock ok [PWRAP] pwrap_init---- debug: init_dio ok [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=0 rdata=6886 at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=1 rdata=6986 at times=8 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=2 rdata=E55A at times=11 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=3 rdata=E55A at times=11 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=8 rdata=A21A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=9 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=10 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=11 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=12 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=13 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=14 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=15 rdata=A65A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=16 rdata=886A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=17 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=18 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe [Read Test of MT6351] tuning,index=19 rdata=996A at times=0 [PWRAP] _pwrap_init_sistrobe best point,at index=7 [PWRAP] pwrap_init---- strobe ok [PWRAP] mt_pwrap_init---- init_chiper1 [PWRAP] mt_pwrap_init---- init_chiper2 [PWRAP] mt_pwrap_init---- init_chiper3 [PWRAP] pwrap_init---- Cipher ok [PWRAP] pwrap_init---- adc_set ok [PWRAP] pwrap_init---- priority ok [PWRAP] pwrap_init---- wacs enable ok [PWRAP] Preloader PMIC_WRAP_WACS_P2P_EN=1 [PWRAP] Preloader PMIC_WRAP_INIT_DONE_P2P=1 [PWRAP] Preloader pwrap_init Done!!!!!!!!! [PWRAP] after MT6351 pwrap_write [PWRAP] write MT6351 Test pass [PWRAP] Read MT6351 Test pass,return_value=0 [PMIC_WRAP]wrap_init pass,the return value=0. DATE_CODE_YY:0, DATE_CODE_WW:0 [SegCode] CS, PROJECT_CODE:0x1A8D, FUNCTION_CODE_0:0x0, FUNCTION_CODE_1:0x0, FAB_CODE:0x0 [LDO] 0:0x8979AB79, 1:0x0, 2:0x78A90000, 3:0xBA999 [PMIC_PRELOADER] Preloader Start.................. [PMIC_PRELOADER] MT6351 CHIP Code = 0x5120 [PMIC_PRELOADER][pmic_status] Reg[0x2BC]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21E]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21A]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x21C]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x212]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x214]=0x0 [PMIC_PRELOADER][pmic_status] Reg[0x18]=0x8000 [PMIC_PRELOADER][pmic_status] Reg[0x2B6]=0x204 [PMIC_PRELOADER][pmic_status] Reg[0x2A6]=0xC6C [PMIC_PRELOADER]just_rst = 0 ignore bat check [PMIC_PRELOADER] turn off usbdl wo battery.................. [PMIC_PRELOADER][6351] is_efuse_trimed=0x1,[0xC5C]=0x8000 [PMIC_PRELOADER][6351] efuse_data[0x0]=0x21E3 [PMIC_PRELOADER][6351] efuse_data[0x1]=0x3 [PMIC_PRELOADER][6351] efuse_data[0x2]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x3]=0xBFE0 [PMIC_PRELOADER][6351] efuse_data[0x4]=0xBD54 [PMIC_PRELOADER][6351] efuse_data[0x5]=0x3FE [PMIC_PRELOADER][6351] efuse_data[0x6]=0x1620 [PMIC_PRELOADER][6351] efuse_data[0x7]=0x3C [PMIC_PRELOADER][6351] efuse_data[0x8]=0x43C [PMIC_PRELOADER][6351] efuse_data[0x9]=0x5000 [PMIC_PRELOADER][6351] efuse_data[0xA]=0x8081 [PMIC_PRELOADER][6351] efuse_data[0xB]=0x4C [PMIC_PRELOADER][6351] efuse_data[0xC]=0x9000 [PMIC_PRELOADER][6351] efuse_data[0xD]=0xC342 [PMIC_PRELOADER][6351] efuse_data[0xE]=0x2223 [PMIC_PRELOADER][6351] efuse_data[0xF]=0x9244 [PMIC_PRELOADER][6351] efuse_data[0x10]=0x36 [PMIC_PRELOADER][6351] efuse_data[0x11]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x12]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x13]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x14]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x15]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x16]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x17]=0x4 [PMIC_PRELOADER][6351] efuse_data[0x18]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x19]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1A]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1B]=0x0 [PMIC_PRELOADER][6351] efuse_data[0x1C]=0x727F [PMIC_PRELOADER][6351] efuse_data[0x1D]=0xC81E [PMIC_PRELOADER][6351] efuse_data[0x1E]=0xD6F0 [PMIC_PRELOADER][6351] efuse_data[0x1F]=0x0 [PMIC_PRELOADER][pmic_init] Reg[0x2B6]=0x205 [fan53555_hw_component_detect] exist = 1, Chip ID = 8001 [fan53555_driver_probe] fan53555_hw_init [0x0]=0x28 [0x1]=0x2C [0x2]=0x80 [0x3]=0x80 [0x4]=0x1 [0x5]=0x0 [fan53555_driver_probe] PL g_fan53555_hw_exist=1, g_fan53555_driver_ready=1 [fan53555_driver_probe] PL No I2C_EXT_BUCK_CHANNEL (7) [fan53555_driver_probe] PL No GPIO_EXT_BUCK_VSEL_PIN (0x0) [da9214_hw_component_detect] exist=1, Reg[0x105][7:4]=0xD Enable continuous high speed mode Start Enable continuous high speed mode End [da9214_driver_probe] da9214_hw_init [da9214_driver_probe] PL g_da9214_hw_exist=1, g_da9214_driver_ready=1 [da9214_driver_probe] PL No I2C_EXT_BUCK_CHANNEL (6) [da9214_driver_probe] PL No GPIO_EXT_BUCK_VSEL_PIN (0x0) ignore bat check [PMIC_PRELOADER] [pmic_init] Done...................0x04de:0xA4 vproc/vsram run as hw default [HQA]Set NV setting: Vcore = 1000 mV(0x40, should be 0x40), Vdram = 1218 mV(0x63, should be 0x63) [PLFM] Init I2C: OK(0) [PLFM] Init PWRAP: OK(0) [PLFM] Init PMIC: OK(0) [PLFM] chip_ver[0] [PTP] >> ptp_init() [PTP] >> get_devinfo() [PTP] << get_devinfo():322 [PTP] >> ptp_init_det() [PTP] PTP read VBOOT from upmu: 0x00003021 [PTP] VCORE voltage bin to 1.5V [PTP] << ptp_init_det():445 [PTP] PTP set volt: 0x00000058 [PTP] M_HW_RES0 = 0x013C8B73 [PTP] M_HW_RES1 = 0x9A5E5088 [PTP] M_HW_RES2 = 0x43A08000 [PTP] M_HW_RES3 = 0x00000000 [PTP] M_HW_RES4 = 0x00000000 [PTP] M_HW_RES5 = 0x00000000 [PTP] << ptp_init():1040 [BLDR] Build Time: 20160513-222351 [DDR Reserve] ddr reserve mode not be enabled yet ==== Dump RGU Reg ======== RGU MODE: 5D RGU LENGTH: FFE0 RGU STA: A0000000 RGU INTERVAL: FFF RGU SWSYSRST: 10000 RGU DEBUG_CTL: 200F3 RGU LATCH_CTL: F1417 RGU DEBUG1: A0000000 ==== Dump RGU Reg End ==== RGU: g_rgu_satus:5 mtk_wdt_mode_config mode value=10, tmp:22000010 PL RGU RST: ?? SW reset with bypass power key flag Find bypass powerkey flag mtk_wdt_mode_config mode value=5D, tmp:2200005D RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(200F3), MTK_WDT_LATCH_CTL(F1417) WDT IRQ_EN=0x300004 WDT REQ_EN=0x380002 Enter mtk_kpd_gpio_set! after set KP enable: KP_SEL = 0x1C70 ! before clk_buf_enable_clkbuf4: 0x1022B100 = 0x1867775 clk_buf_enable_clkbuf4: 0x1022B100 = 0x1867775 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=3968 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2 [RTC] bbpu = 0xD, con = 0x486, osc32con = 0x7A00, sec = 0x5E7, yea = 0xC002 [RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 [RTC] rtc_boot_check Writeif_unlock [RTC] RTC_SPAR0=0x40 [RTC] rtc_2sec_reboot_check 0x5E7 [RTC] rtc_2sec_stat_clear [RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x40, spar1 = 0x800 [RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1 [RTC] bbpu = 0xD, con = 0x486, cali = 0x5E7 SW reset with bypass power key flag SW reset with bypass power key flag [PLFM] WDT reboot bypass power key! [RTC] enable_dcxo first bbpu = 0xD, con = 0x486, osc32con = 0x7B00, sec = 0x5E7, yea = 0xC002 [RTC] rtc_bbpu_power_on done [RTC] rtc_enable_2sec_reboot config 0x5E7 EMI_MPUX=1 1st EMI_MPUX=0 2nd [EMI] mcp_dram_num:0,discrete_dram_num:1,enable_combo_dis:0 [Everest] ETT version 0.0.9.7 [DramcSwImpedanceCal] Start ======= K DRVP===================== 1. OCD DRVP calibration OK! DRVP=7 ======= K ODTN===================== 3. OCD ODTN calibration OK! ODTN=9 [DramcSwImpedanceCal] Done [is_pll_good] PLL 100 good [DdrPhyInit] ====Begin: Freq=400 ==== [DdrPhyInit] ====Done==== [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank1 [DdrUpdateACTiming] match AC timing 4 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 2, (u1Multi 1), Rank 1 [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=0, Rank=1 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF FF FF FF 11 FF FF FF FF 12 FF FF FF FF 13 FF FF FF FF 14 FF FF FF FF 15 FF FF FF FF 16 FF FF FF FF 17 FF FF FF FF 18 FF FF FF FF 19 FF FF FF FF 20 FF FF FF FF 21 FF FF FF FF 22 FF FF FF FF 23 FF FF FF FF 24 FF FF FF FF 25 FF FF FF FF 26 FF FF FF FF 27 FF FF FF FF 28 FF FF FF FF 29 FF FF FF FF 30 FF FF FF FF 31 FF FF FF FF 32 FF FF FF FF 33 FF FF FF FF 34 FF FF FF FF 35 FF FF FF FF 36 FF FF FF FF 37 FF FF FF FF 38 FF FF FF FF 39 FF FF FF FF 40 FF FF FF FF 41 FF FF FF FF 42 FF FF FF FF 43 FF FF FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF 54 FF FF FF FF 55 FF FF FF FF 56 FF FF FF FF 57 FF FF FF FF 58 FF FF FF FF 59 FF FF FF FF 60 FF FF FF FF 61 FF FF FF FF 62 FF FF FF FF 63 FF FF FF FF 64 FF FF FF FF 65 FF FF FF FF 66 FF FF FF FF 67 FF FF FF FF 68 FF FF FF FF 69 FF FF FF FF 70 FF FF FF FF 71 FF FF FF FF 72 FF FF FF FF 73 FF FF FF FF 74 FF FF FF FF 75 FF FF FF FF 76 FF FF FF FF 77 FF FF FF FF 78 FF FF FF FF 79 FF FF FF FF 80 FF FF FF FF 81 FF FF FF FF 82 FF FF FF FF 83 FF FF FF FF pass bytecount = 0xF0 (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 0 DQS1 delay = 0 DQS2 delay = 0 DQS3 delay = 0 DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank1 [DramcWriteLeveling] ====Done==== [DramRankNumberDetection] 1, 00000008 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming] match AC timing 4 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=400, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 1 1 0 0 0 0 1, | 1 1 1 1 1 0 0 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 1 1 1 1 32, | 0 0 0 0 1 1 1 0 33, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~31) 15, CA1 (0~31) 15, CA2 (0~31) 15, CA3 (0~31) 15, CA5 (1~32) 16, CA6 (2~32) 17, CA7 (2~32) 17, CA8 (1~31) 16, ========================================= [CA Training] Frequency=400, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 1 33, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~31) 15, CA9 (1~32) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 0 0 0 0 11 0 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 0 0 0 0 25 0 0 0 0 26 0 0 0 0 27 0 FF 0 0 28 0 0 0 0 29 0 FF 0 0 30 0 FF 0 0 31 0 FF 0 0 32 0 FF 0 0 33 0 FF 0 FF 34 0 FF 0 0 35 0 FF 0 FF 36 0 FF 0 0 37 0 FF 0 0 38 0 FF 0 FF 39 0 FF 0 FF 40 0 FF 0 FF 41 0 FF 0 FF 42 0 FF 0 FF 43 FF FF FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 43 DQS1 delay = 29 DQS2 delay = 43 DQS3 delay = 38 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=400, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 1 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 2 |(B3->B0) 0x1111, 0x1211, 0x1110, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1211, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1110, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 1 10 |(B3->B0) 0x1010, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 1 12 |(B3->B0) 0x1010, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 20 |(B3->B0) 0x1211, 0x0E0E, 0x1211, 0x0E0E | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 22 |(B3->B0) 0x1211, 0x1010, 0x1211, 0x1010 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x1211, 0x1211, 0x1212, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 3 0 |(B3->B0) 0x1211, 0x1211, 0x1313, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x1211, 0x1211, 0x1615, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 4 |(B3->B0) 0x1211, 0x1211, 0x1616, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 6 |(B3->B0) 0x1212, 0x1211, 0x2222, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 8 |(B3->B0) 0x1D1D, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 3, 8) 1 3 10 |(B3->B0) 0x1E1D, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 3 12 |(B3->B0) 0x2121, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 3 14 |(B3->B0) 0x2323, 0x1514, 0x2323, 0x1515 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 3, 14) 1 3 16 |(B3->B0) 0x2323, 0x1514, 0x2323, 0x1514 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 18 |(B3->B0) 0x2323, 0x1F1F, 0x2323, 0x1E1E | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 20 |(B3->B0) 0x2323, 0x2121, 0x2323, 0x2121 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 3, 22) [Byte 2]First pass (1, 3, 22) 1 3 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 5 0 |(B3->B0) 0x2323, 0x2323, 0x1C1C, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 8) Pass tap=28 1 5 2 |(B3->B0) 0x2323, 0x2323, 0x1A19, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 5 4 |(B3->B0) 0x2323, 0x2323, 0x1A19, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 5 6 |(B3->B0) 0x1E1E, 0x2323, 0x2322, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 3, 14) Pass tap=28 1 5 8 |(B3->B0) 0x1F1E, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 10 |(B3->B0) 0x2121, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 12 |(B3->B0) 0x2221, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 5 14 |(B3->B0) 0x2322, 0x2121, 0x2322, 0x2221 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 3, 22) Pass tap=28 [Byte 2]Bigger pass win(1, 3, 22) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 4, 18) best DQS1 delay(2T, 0.5T, PI) = (1, 4, 4) best DQS2 delay(2T, 0.5T, PI) = (1, 4, 18) best DQS3 delay(2T, 0.5T, PI) = (1, 4, 10) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 18) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 4) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 18) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 10) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=400, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x10 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0x00000000, sum=1 15, 0x00000000, sum=2 16, 0x00000000, sum=3 17, 0x00000000, sum=4 18, 0x00000000, sum=5 pattern=5 first_step=14 total pass=6 best_step=16 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 400 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 ====DramcRxdqsGatingPostProcess (Rank = 0) ======================================== best DQS0 delay(2T, 0.5T) = (1, 0) best DQS1 delay(2T, 0.5T) = (1, 0) best DQS2 delay(2T, 0.5T) = (1, 0) best DQS3 delay(2T, 0.5T) = (1, 0) best DQS0 P1 delay(2T, 0.5T) = (1, 2) best DQS1 P1 delay(2T, 0.5T) = (1, 2) best DQS2 P1 delay(2T, 0.5T) = (1, 2) best DQS3 P1 delay(2T, 0.5T) = (1, 2) TX_dly_DQSgated check: min 2 max 2, s1ChangeDQSINCTL=-1 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=7 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=400, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 0 0 0 0 0 0 0 1 1, | 0 0 0 1 1 1 1 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 1 1 1 1 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (2~31) 16, CA1 (2~31) 16, CA2 (2~31) 16, CA3 (1~31) 16, CA5 (1~31) 16, CA6 (1~31) 16, CA7 (1~31) 16, CA8 (0~31) 15, ========================================= [CA Training] Frequency=400, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 0 1 1, | 0 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (2~31) 16, CA9 (0~31) 15, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=400, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF FF FF 1 0 FF 0 0 2 0 FF 0 0 3 0 FF 0 FF 4 0 FF 0 0 5 0 0 0 0 6 0 0 0 0 7 0 FF 0 0 8 0 0 0 0 9 0 0 0 0 10 0 0 0 0 11 0 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 FF 0 0 0 24 FF 0 0 0 25 0 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 FF 0 30 FF 0 FF 0 31 FF 0 0 0 32 FF 0 FF 0 33 FF 0 FF 0 34 FF FF FF FF 35 FF 0 FF FF 36 FF FF FF FF 37 FF 0 FF 0 38 FF FF FF FF 39 FF FF FF FF 40 FF FF FF FF 41 FF FF FF FF 42 FF FF FF FF 43 FF FF FF FF 44 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 26 DQS1 delay = 38 DQS2 delay = 32 DQS3 delay = 38 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=400, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 1 0 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1110 | 11 11 00 00 11 11 11 11 | 0x00000000 1 1 2 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1211, 0x0F0F, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1211, 0x1010, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x1111, 0x1110, 0x1111, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 10 |(B3->B0) 0x0F0E, 0x1211, 0x0E0D, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 12 |(B3->B0) 0x0E0D, 0x1211, 0x100F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x1111, 0x1211, 0x1111, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1615 | 11 11 11 11 11 11 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1818 | 11 11 11 11 11 11 00 00 | 0x00000000 1 3 0 |(B3->B0) 0x1211, 0x1413, 0x1211, 0x1F1F | 11 11 11 11 11 11 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x1211, 0x1212, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 3, 2) 1 3 4 |(B3->B0) 0x1211, 0x1B1B, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 6 |(B3->B0) 0x1211, 0x2121, 0x1312, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 3 8 |(B3->B0) 0x1615, 0x2323, 0x1717, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 [Byte 2]First pass (1, 3, 8) 1 3 10 |(B3->B0) 0x1F1F, 0x2323, 0x2020, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 12 |(B3->B0) 0x1817, 0x2323, 0x1D1D, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 1 3 14 |(B3->B0) 0x2020, 0x2323, 0x2121, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 16 |(B3->B0) 0x2322, 0x2323, 0x2323, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 3, 16) 1 3 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 3]First pass (1, 3, 18) 1 3 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 3 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 4 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1F1F | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 3, 2) Pass tap=28 1 4 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1F1E | 00 00 00 00 00 00 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x1E1E | 00 00 11 11 00 00 00 00 | 0x00000000 [Byte 2]Bigger pass win(1, 3, 8) Pass tap=27 1 5 0 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2020 | 00 00 11 11 00 00 11 11 | 0x00000000 1 5 2 |(B3->B0) 0x2323, 0x1B1B, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x2323, 0x1B1B, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x2323, 0x2020, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 5 8 |(B3->B0) 0x1F1E, 0x2322, 0x1E1D, 0x2322 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 3, 16) Pass tap=28 [Byte 3]Bigger pass win(1, 3, 18) Pass tap=27 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 3, 30) best DQS1 delay(2T, 0.5T, PI) = (1, 4, 12) best DQS2 delay(2T, 0.5T, PI) = (1, 4, 3) best DQS3 delay(2T, 0.5T, PI) = (1, 4, 13) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 5, 30) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 12) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 3) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 13) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=400, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x10 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0x00000000, sum=1 15, 0x00000000, sum=2 16, 0x00000000, sum=3 17, 0x00000000, sum=4 18, 0x00000000, sum=5 pattern=5 first_step=14 total pass=6 best_step=16 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 400 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=2, RANKINCTL=0, u4XRTR2R=8 [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Channel 0, Rank 0, Desity 40000000. [GetDramInforAfterCalByMRR] Channel 1, Rank 0, Desity 40000000. [EMI] MDL number = 0 DdrPhySetting_Everest_LP3()+DramcSetting_Everest_LP3() Save frequency registers setting into shuffle register. [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming] match AC timing 2 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=635, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 1 1 0 0 0 0 1, | 1 1 1 1 1 0 0 1 2, | 1 1 1 1 1 1 0 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 0 0 0 0 1 1 1 1 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~30) 15, CA1 (0~30) 15, CA2 (0~30) 15, CA3 (0~30) 15, CA5 (1~31) 16, CA6 (2~31) 16, CA7 (3~31) 17, CA8 (1~31) 16, ========================================= [CA Training] Frequency=635, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 0 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~31) 15, CA9 (2~31) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=635, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF 0 FF 0 11 FF 0 FF 0 12 FF 0 FF 0 13 FF 0 FF 0 14 FF 0 0 0 15 FF 0 FF 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 0 FF 0 0 25 0 FF 0 0 26 0 FF 0 0 27 0 FF 0 0 28 0 FF 0 0 29 0 FF 0 0 30 0 FF 0 0 31 0 FF 0 0 32 0 FF 0 0 33 0 FF 0 0 34 0 FF 0 0 35 0 FF 0 FF 36 0 FF 0 0 37 0 FF 0 FF 38 0 FF 0 FF 39 0 FF 0 FF 40 0 FF 0 FF 41 0 FF 0 FF 42 0 FF 0 FF 43 0 FF 0 FF 44 0 FF 0 FF 45 0 FF 0 FF 46 0 FF 0 FF 47 FF FF FF FF 48 FF FF FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 47 DQS1 delay = 24 DQS2 delay = 47 DQS3 delay = 37 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=635, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 0 7 0 |(B3->B0) 0x1211, 0x1211, 0x1111, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 2 |(B3->B0) 0x1010, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 4 |(B3->B0) 0x1110, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 6 |(B3->B0) 0x0F0F, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 0 7 8 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 0 7 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 16 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1111 | 11 11 00 00 11 11 11 11 | 0x00000000 0 7 18 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x1010 | 11 11 11 11 11 11 00 00 | 0x00000000 0 7 20 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 22 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1010 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 24 |(B3->B0) 0x1211, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 26 |(B3->B0) 0x1211, 0x1211, 0x0E0D, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 28 |(B3->B0) 0x1211, 0x1211, 0x1D1D, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 30 |(B3->B0) 0x1211, 0x1211, 0x2020, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 1 0 |(B3->B0) 0x1211, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 1, 0) 1 1 2 |(B3->B0) 0x1212, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 4 |(B3->B0) 0x1514, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 6 |(B3->B0) 0x1D1D, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 8 |(B3->B0) 0x2322, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 1 10 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 1, 10) 1 1 12 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 14 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 16 |(B3->B0) 0x2323, 0x1313, 0x2323, 0x1312 | 00 00 00 00 00 00 11 11 | 0x00000000 1 1 18 |(B3->B0) 0x2323, 0x1515, 0x2323, 0x1615 | 00 00 00 00 00 00 11 11 | 0x00000000 1 1 20 |(B3->B0) 0x2323, 0x1D1C, 0x2323, 0x1A1A | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 22 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2121 | 00 00 11 11 00 00 11 11 | 0x00000000 1 1 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 1, 24) [Byte 2]First pass (1, 1, 24) 1 1 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 22 |(B3->B0) 0x2323, 0x2323, 0x2222, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 1, 0) Pass tap=27 1 2 24 |(B3->B0) 0x2323, 0x2323, 0x1C1B, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 2 26 |(B3->B0) 0x2323, 0x2323, 0x1818, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 28 |(B3->B0) 0x2323, 0x2323, 0x2120, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 2 30 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 1, 10) Pass tap=26 1 3 0 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 2 |(B3->B0) 0x201F, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 4 |(B3->B0) 0x1D1C, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 6 |(B3->B0) 0x1D1D, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 8 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 10 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 12 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 14 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 3 16 |(B3->B0) 0x2322, 0x2221, 0x2322, 0x2222 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 1, 24) Pass tap=28 [Byte 2]Bigger pass win(1, 1, 24) Pass tap=28 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 2, 20) best DQS1 delay(2T, 0.5T, PI) = (1, 1, 27) best DQS2 delay(2T, 0.5T, PI) = (1, 2, 20) best DQS3 delay(2T, 0.5T, PI) = (1, 2, 4) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 4, 20) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 3, 27) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 4, 20) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 4, 4) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=635, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x12 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0x00000000, sum=1 17, 0x00000000, sum=2 18, 0x00000000, sum=3 19, 0x00000000, sum=4 20, 0x00000000, sum=5 pattern=5 first_step=16 total pass=6 best_step=18 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 635 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=9 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=635, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 0 0 0 0 0 0 0 1 1, | 0 0 0 0 1 1 1 1 2, | 0 0 0 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 1 1 1 1 0 0 0 0 32, | 1 1 1 0 0 0 0 0 33, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (3~32) 17, CA1 (3~32) 17, CA2 (3~32) 17, CA3 (2~31) 16, CA5 (1~30) 15, CA6 (1~30) 15, CA7 (1~30) 15, CA8 (0~30) 15, ========================================= [CA Training] Frequency=635, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 0 1 1, | 0 1 2, | 0 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 0 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (3~31) 17, CA9 (0~30) 15, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 Clk Dealy is 0, CA delay is 15 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=635, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF 0 FF 1 0 FF 0 FF 2 0 FF 0 FF 3 0 FF 0 FF 4 0 FF 0 FF 5 0 FF 0 0 6 0 FF 0 FF 7 0 FF 0 0 8 0 0 0 0 9 0 FF 0 0 10 0 0 0 0 11 0 0 0 0 12 0 0 0 0 13 0 0 0 0 14 0 0 0 0 15 0 0 0 0 16 0 0 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 FF 0 0 0 21 FF 0 0 0 22 FF 0 0 0 23 FF 0 0 0 24 FF 0 0 0 25 FF 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 0 0 30 FF 0 FF 0 31 FF 0 FF 0 32 FF 0 FF 0 33 FF 0 FF 0 34 FF 0 FF 0 35 FF 0 FF 0 36 FF 0 FF 0 37 FF 0 FF 0 38 FF 0 FF 0 39 FF 0 FF FF 40 FF FF FF FF 41 FF 0 FF FF 42 FF FF FF FF 43 FF FF FF FF 44 FF FF FF FF 45 FF FF FF FF 46 FF FF FF FF 47 FF FF FF FF 48 0 FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 20 DQS1 delay = 42 DQS2 delay = 30 DQS3 delay = 39 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=635, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 0 7 0 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 8 |(B3->B0) 0x0F0F, 0x1211, 0x0E0E, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 0 7 10 |(B3->B0) 0x0D0D, 0x1211, 0x0F0F, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 0 7 12 |(B3->B0) 0x0E0E, 0x1211, 0x1111, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 14 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 0 7 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1110 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x100F | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1716 | 11 11 11 11 11 11 11 11 | 0x00000000 1 0 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1A1A | 11 11 11 11 11 11 00 00 | 0x00000000 1 0 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 0, 24) 1 0 26 |(B3->B0) 0x1211, 0x1010, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 0 28 |(B3->B0) 0x1211, 0x100F, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 0 30 |(B3->B0) 0x1211, 0x1918, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 0 |(B3->B0) 0x1211, 0x201F, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 1 2 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 2]First pass (1, 1, 2) 1 1 4 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 6 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 8 |(B3->B0) 0x1212, 0x2323, 0x1413, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 10 |(B3->B0) 0x1918, 0x2323, 0x1E1E, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 12 |(B3->B0) 0x1E1D, 0x2323, 0x201F, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 1 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 1, 14) [Byte 3]First pass (1, 1, 14) 1 1 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 1 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 2 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2120 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 0, 24) Pass tap=28 1 2 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1C1C | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1B1A | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1F1F | 00 00 00 00 00 00 11 11 | 0x00000000 1 2 24 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 2]Bigger pass win(1, 1, 2) Pass tap=27 1 2 26 |(B3->B0) 0x2323, 0x2222, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 2 28 |(B3->B0) 0x2323, 0x1B1B, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 2 30 |(B3->B0) 0x2323, 0x1C1B, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 0 |(B3->B0) 0x2323, 0x2221, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 2 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 4 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 6 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 1 3 8 |(B3->B0) 0x1E1D, 0x2322, 0x1D1D, 0x2322 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 1, 14) Pass tap=29 [Byte 3]Bigger pass win(1, 1, 14) Pass tap=29 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 1, 20) best DQS1 delay(2T, 0.5T, PI) = (1, 2, 11) best DQS2 delay(2T, 0.5T, PI) = (1, 1, 29) best DQS3 delay(2T, 0.5T, PI) = (1, 2, 11) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (1, 3, 20) best DQS1 P1 delay(2T, 0.5T, PI) = (1, 4, 11) best DQS2 P1 delay(2T, 0.5T, PI) = (1, 3, 29) best DQS3 P1 delay(2T, 0.5T, PI) = (1, 4, 11) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=635, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x12 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFF3FFF00, sum=0 16, 0x00000000, sum=1 17, 0x00000000, sum=2 18, 0x00000000, sum=3 19, 0x00000000, sum=4 20, 0x00000000, sum=5 pattern=5 first_step=16 total pass=6 best_step=18 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 635 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 TX_dly_DQSgated check: min 2 max 3, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=9 Save frequency registers setting into shuffle register. [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcInit] ====Begin==== DramcModeRegInit_Everest_LP3 for Rank0 [DdrUpdateACTiming_EMI] match AC timing 1 [DramcInit] ====Done==== [LJ_PHYPLL_0], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_1], PASS=0, FAIL=0, BAND=00 [LJ_PHYPLL_2], PASS=0, FAIL=0, BAND=00 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=800, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 1 1 0 1 0 0 0 0 1, | 1 1 1 1 1 1 0 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 0 1 0 1 1 1 1 30, | 1 1 1 1 1 1 1 1 31, | 0 0 1 0 1 1 1 1 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (0~30) 15, CA1 (0~28) 14, CA2 (1~31) 16, CA3 (0~28) 14, CA5 (1~31) 16, CA6 (1~31) 16, CA7 (2~31) 16, CA8 (1~31) 16, ========================================= [CA Training] Frequency=800, Channel=0, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 0 0, | 1 0 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 0 1 31, | 0 1 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (0~29) 14, CA9 (1~31) 16, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 LP3_JV_WORKAROUND: sepcial setting, CA delay fine-tune (15->13)n Clk Dealy is 0, CA delay is 13 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=800, Channel=0, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 10 FF 0 FF 0 11 FF 0 FF FF 12 FF 0 FF FF 13 FF 0 FF 0 14 FF 0 FF FF 15 FF 0 FF 0 16 FF 0 FF 0 17 FF 0 FF 0 18 FF 0 FF 0 19 FF 0 FF 0 20 FF 0 FF 0 21 FF 0 FF 0 22 FF 0 FF 0 23 FF 0 FF 0 24 FF 0 FF 0 25 FF 0 FF 0 26 FF 0 FF 0 27 FF 0 FF 0 28 FF 0 FF 0 29 FF 0 0 0 30 FF FF 0 0 31 FF 0 0 0 32 0 FF 0 0 33 0 FF 0 0 34 0 FF 0 0 35 0 FF 0 0 36 0 FF 0 0 37 0 FF 0 0 38 0 FF 0 0 39 0 FF 0 0 40 0 FF 0 0 41 0 FF 0 0 42 0 FF 0 0 43 0 FF 0 FF 44 0 FF 0 FF 45 0 FF 0 FF 46 0 FF 0 FF 47 0 FF 0 FF 48 0 FF 0 FF 49 0 FF 0 FF 50 0 FF 0 FF 51 0 FF 0 FF 52 0 FF 0 FF 53 0 FF 0 FF 54 0 FF 0 FF 55 0 FF 0 FF 56 0 FF 0 FF 57 0 FF 0 FF 58 0 FF 0 FF 59 0 FF 0 FF 60 0 FF 0 FF 61 0 FF 0 FF 62 FF 0 FF FF 63 0 FF 0 FF 64 FF 0 FF FF 65 FF FF FF FF 66 FF 0 FF FF 67 FF 0 FF FF 68 FF 0 FF FF 69 FF 0 FF FF 70 FF 0 FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 64 DQS1 delay = 32 DQS2 delay = 64 DQS3 delay = 43 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=800, Channel=0, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 4 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 2 |(B3->B0) 0x1211, 0x1211, 0x1111, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 4 |(B3->B0) 0x1211, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 6 |(B3->B0) 0x1211, 0x1211, 0x0B0A, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 8 |(B3->B0) 0x1211, 0x1211, 0x0C0B, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 10 |(B3->B0) 0x1211, 0x1211, 0x1010, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 4 12 |(B3->B0) 0x1211, 0x1211, 0x1111, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 4 14 |(B3->B0) 0x1110, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 16 |(B3->B0) 0x0E0E, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 18 |(B3->B0) 0x0C0C, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 4 20 |(B3->B0) 0x0D0D, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 22 |(B3->B0) 0x1010, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 4 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 2 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x1110 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1111 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x1211, 0x0F0E, 0x1211, 0x0F0F | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 8 |(B3->B0) 0x1211, 0x0E0D, 0x1211, 0x0C0B | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 10 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1111 | 11 11 11 11 11 11 00 00 | 0x00000000 1 5 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 2 |(B3->B0) 0x1211, 0x1211, 0x1111, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 6 |(B3->B0) 0x1211, 0x1211, 0x1313, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 8 |(B3->B0) 0x1211, 0x1211, 0x1A19, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 10 |(B3->B0) 0x1211, 0x1211, 0x201F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 12 |(B3->B0) 0x1211, 0x1211, 0x2322, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 14 |(B3->B0) 0x1111, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 [Byte 1]First pass (1, 6, 14) 1 6 16 |(B3->B0) 0x1211, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 18 |(B3->B0) 0x1716, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 20 |(B3->B0) 0x1514, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 22 |(B3->B0) 0x1F1F, 0x1211, 0x2323, 0x1211 | 11 11 11 11 00 00 11 11 | 0x00000000 1 6 24 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 3]First pass (1, 6, 24) 1 6 26 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 6 28 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 6 30 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 0 |(B3->B0) 0x2323, 0x1211, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 2 |(B3->B0) 0x2323, 0x1212, 0x2323, 0x1211 | 00 00 11 11 00 00 11 11 | 0x00000000 1 7 4 |(B3->B0) 0x2323, 0x1312, 0x2323, 0x1313 | 00 00 11 11 00 00 00 00 | 0x00000000 1 7 6 |(B3->B0) 0x2323, 0x1817, 0x2323, 0x1717 | 00 00 11 11 00 00 00 00 | 0x00000000 1 7 8 |(B3->B0) 0x2323, 0x1B1A, 0x2323, 0x1A1A | 00 00 11 11 00 00 00 00 | 0x00000000 1 7 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 0]First pass (1, 7, 10) [Byte 2]First pass (1, 7, 10) 1 7 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 4 |(B3->B0) 0x2323, 0x2323, 0x1818, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 [Byte 1]Bigger pass win(1, 6, 14) Pass tap=27 2 0 6 |(B3->B0) 0x2323, 0x2323, 0x1717, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 8 |(B3->B0) 0x2323, 0x2323, 0x1918, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 10 |(B3->B0) 0x2323, 0x2323, 0x1E1D, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 12 |(B3->B0) 0x2323, 0x2323, 0x2221, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 14 |(B3->B0) 0x2222, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 3]Bigger pass win(1, 6, 24) Pass tap=27 2 0 16 |(B3->B0) 0x1B1B, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 18 |(B3->B0) 0x1919, 0x2323, 0x2322, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 2 0 20 |(B3->B0) 0x1716, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 22 |(B3->B0) 0x2120, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 24 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 26 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 28 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 0 30 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 1 0 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 1 2 |(B3->B0) 0x2322, 0x2323, 0x2322, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 2 1 4 |(B3->B0) 0x2322, 0x1E1E, 0x2322, 0x1F1E | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 7, 10) Pass tap=29 [Byte 2]Bigger pass win(1, 7, 10) Pass tap=29 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=0(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (2, 0, 7) best DQS1 delay(2T, 0.5T, PI) = (1, 7, 9) best DQS2 delay(2T, 0.5T, PI) = (2, 0, 7) best DQS3 delay(2T, 0.5T, PI) = (1, 7, 19) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (2, 2, 7) best DQS1 P1 delay(2T, 0.5T, PI) = (2, 1, 9) best DQS2 P1 delay(2T, 0.5T, PI) = (2, 2, 7) best DQS3 P1 delay(2T, 0.5T, PI) = (2, 1, 19) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=800, Channel=0, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x13 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0xFFFFFFFF, sum=0 17, 0x000000E0, sum=0 18, 0x00000000, sum=1 19, 0x00000000, sum=2 20, 0x00000000, sum=3 21, 0x00000000, sum=4 22, 0x00000000, sum=5 pattern=5 first_step=18 total pass=6 best_step=20 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 800 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3 TX_dly_DQSgated check: min 3 max 4, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=10 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 [CATrainingLP3] Begin ========================================= [CA Training] Frequency=800, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA0~CA3, CA5~8 ========================================= -15, | 0 0 0 0 0 0 0 0 -14, | 0 0 0 0 0 0 0 0 -13, | 0 0 0 0 0 0 0 0 -12, | 0 0 0 0 0 0 0 0 -11, | 0 0 0 0 0 0 0 0 -10, | 0 0 0 0 0 0 0 0 -9, | 0 0 0 0 0 0 0 0 -8, | 0 0 0 0 0 0 0 0 -7, | 0 0 0 0 0 0 0 0 -6, | 0 0 0 0 0 0 0 0 -5, | 0 0 0 0 0 0 0 0 -4, | 0 0 0 0 0 0 0 0 -3, | 0 0 0 0 0 0 0 0 -2, | 0 0 0 0 0 0 0 0 -1, | 0 0 0 0 0 0 0 0 0, | 0 0 0 0 1 1 1 1 1, | 0 0 0 1 1 1 1 1 2, | 1 1 1 1 1 1 1 1 3, | 1 1 1 1 1 1 1 1 4, | 1 1 1 1 1 1 1 1 5, | 1 1 1 1 1 1 1 1 6, | 1 1 1 1 1 1 1 1 7, | 1 1 1 1 1 1 1 1 8, | 1 1 1 1 1 1 1 1 9, | 1 1 1 1 1 1 1 1 10, | 1 1 1 1 1 1 1 1 11, | 1 1 1 1 1 1 1 1 12, | 1 1 1 1 1 1 1 1 13, | 1 1 1 1 1 1 1 1 14, | 1 1 1 1 1 1 1 1 15, | 1 1 1 1 1 1 1 1 16, | 1 1 1 1 1 1 1 1 17, | 1 1 1 1 1 1 1 1 18, | 1 1 1 1 1 1 1 1 19, | 1 1 1 1 1 1 1 1 20, | 1 1 1 1 1 1 1 1 21, | 1 1 1 1 1 1 1 1 22, | 1 1 1 1 1 1 1 1 23, | 1 1 1 1 1 1 1 1 24, | 1 1 1 1 1 1 1 1 25, | 1 1 1 1 1 1 1 1 26, | 1 1 1 1 1 1 1 1 27, | 1 1 1 1 1 1 1 1 28, | 1 1 1 1 1 1 1 1 29, | 1 1 1 1 1 1 1 1 30, | 1 1 1 1 1 1 1 0 31, | 1 1 1 1 1 1 1 0 32, | 0 0 0 0 0 0 0 0 [CATrainingDelayCompare] Early break, uiMR41=1, uiFinishCount=8 CA0 (2~31) 16, CA1 (2~31) 16, CA2 (2~31) 16, CA3 (1~31) 16, CA5 (0~31) 15, CA6 (0~31) 15, CA7 (0~31) 15, CA8 (0~29) 14, ========================================= [CA Training] Frequency=800, Channel=1, Rank=0 x=Pass window CA(max~min) Clk(min~max) center. y=CA4 CA9 ========================================= -15, | 0 0 -14, | 0 0 -13, | 0 0 -12, | 0 0 -11, | 0 0 -10, | 0 0 -9, | 0 0 -8, | 0 0 -7, | 0 0 -6, | 0 0 -5, | 0 0 -4, | 0 0 -3, | 0 0 -2, | 0 0 -1, | 0 1 0, | 0 1 1, | 1 1 2, | 1 1 3, | 1 1 4, | 1 1 5, | 1 1 6, | 1 1 7, | 1 1 8, | 1 1 9, | 1 1 10, | 1 1 11, | 1 1 12, | 1 1 13, | 1 1 14, | 1 1 15, | 1 1 16, | 1 1 17, | 1 1 18, | 1 1 19, | 1 1 20, | 1 1 21, | 1 1 22, | 1 1 23, | 1 1 24, | 1 1 25, | 1 1 26, | 1 1 27, | 1 1 28, | 1 1 29, | 1 1 30, | 1 1 31, | 1 0 32, | 0 0 [CATrainingDelayCompare] Early break, uiMR41=0, uiFinishCount=2 CA4 (1~31) 16, CA9 (-1~30) 14, ========================================= u4GoldenPattern 0x55555555, iFinalCACLK = 15 LP3_JV_WORKAROUND: sepcial setting, CA delay fine-tune (15->13)n Clk Dealy is 0, CA delay is 13 ========================================= DramcModeRegInit_Everest_LP3 for Rank0 [DramcRankSwap] Rank number 1, (u1Multi 0), Rank 0 Rank 0 write leveling calibration [DramcWriteLeveling] Begin =============================================================================== [Write Leveling] Frequency=800, Channel=1, Rank=0 =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- WriteLevelingMoveDQSInsteadOfCLK 0 0 FF FF FF 1 0 FF FF FF 2 0 FF FF FF 3 0 FF FF FF 4 0 FF FF FF 5 0 FF 0 FF 6 0 FF 0 FF 7 0 FF FF FF 8 0 FF 0 FF 9 0 FF 0 FF 10 0 FF 0 FF 11 0 FF 0 FF 12 0 FF 0 FF 13 0 FF 0 FF 14 0 FF 0 FF 15 0 FF 0 0 16 0 FF 0 0 17 0 0 0 0 18 0 0 0 0 19 0 0 0 0 20 0 0 0 0 21 0 0 0 0 22 0 0 0 0 23 0 0 0 0 24 0 0 0 0 25 FF 0 0 0 26 FF 0 0 0 27 FF 0 0 0 28 FF 0 0 0 29 FF 0 0 0 30 FF 0 0 0 31 FF 0 0 0 32 FF 0 0 0 33 FF 0 0 0 34 FF 0 0 0 35 FF 0 0 0 36 FF 0 0 0 37 FF 0 FF 0 38 FF 0 0 0 39 FF 0 FF 0 40 FF 0 FF 0 41 FF 0 FF 0 42 FF 0 FF 0 43 FF 0 FF 0 44 FF 0 FF 0 45 FF 0 FF 0 46 FF 0 FF 0 47 FF 0 FF 0 48 FF 0 FF FF 49 FF FF FF FF 50 FF FF FF FF 51 FF FF FF FF 52 FF FF FF FF 53 FF FF FF FF 54 FF FF FF FF 55 FF FF FF FF pass bytecount = 0xFF (0xff means all bytes pass) ======================================== WL Clk delay = 0, CA CLK delay = 0 No need to update CA/CS delay because the CLK delay is small than CA training. Final Clk output delay = 0 DQS0 delay = 25 DQS1 delay = 49 DQS2 delay = 39 DQS3 delay = 48 DramcModeRegInit_Everest_LP3 for Rank0 [DramcWriteLeveling] ====Done==== =============================================================================== [Gating] Frequency=800, Channel=1, Rank=0 x = dqs result y = coarse_2T coarse_0.5T finetune ------------------------------------------------------------------------------- y | dqs0f dqs0r dqs1f dqs1r dqs2f dqs2r dqs3f dqs3r ------------------------------------------------------------------------------- 1 4 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x0D0D | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1110 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 6 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 8 |(B3->B0) 0x1211, 0x1111, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 10 |(B3->B0) 0x1211, 0x0B0B, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 12 |(B3->B0) 0x1211, 0x0B0B, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 14 |(B3->B0) 0x1211, 0x1010, 0x1211, 0x1211 | 11 11 00 00 11 11 11 11 | 0x00000000 1 4 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 20 |(B3->B0) 0x1110, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 22 |(B3->B0) 0x1111, 0x1211, 0x1110, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 24 |(B3->B0) 0x0B0A, 0x1211, 0x0B0A, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 26 |(B3->B0) 0x0C0B, 0x1211, 0x100F, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 4 28 |(B3->B0) 0x1111, 0x1211, 0x1211, 0x1211 | 00 00 11 11 11 11 11 11 | 0x00000000 1 4 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 8 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 10 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 12 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 14 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 16 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 18 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 20 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 22 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 24 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 26 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1211 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 28 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 11 11 | 0x00000000 1 5 30 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1212 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 0 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x1A1A | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 2 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2222 | 11 11 11 11 11 11 11 11 | 0x00000000 1 6 4 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 [Byte 0]First pass (1, 6, 4) 1 6 6 |(B3->B0) 0x1211, 0x1211, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 8 |(B3->B0) 0x1211, 0x1110, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 10 |(B3->B0) 0x1211, 0x1716, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 12 |(B3->B0) 0x1211, 0x1818, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 14 |(B3->B0) 0x1211, 0x2322, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 16 |(B3->B0) 0x1211, 0x2221, 0x1211, 0x2323 | 11 11 11 11 11 11 00 00 | 0x00000000 1 6 18 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 [Byte 2]First pass (1, 6, 18) 1 6 20 |(B3->B0) 0x1211, 0x2323, 0x1111, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 22 |(B3->B0) 0x1211, 0x2323, 0x1211, 0x2323 | 11 11 00 00 11 11 00 00 | 0x00000000 1 6 24 |(B3->B0) 0x1413, 0x2323, 0x1515, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 1 6 26 |(B3->B0) 0x1818, 0x2323, 0x1E1D, 0x2323 | 00 00 00 00 11 11 00 00 | 0x00000000 1 6 28 |(B3->B0) 0x2322, 0x2323, 0x2323, 0x2323 | 11 11 00 00 00 00 00 00 | 0x00000000 [Byte 1]First pass (1, 6, 28) 1 6 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 [Byte 3]First pass (1, 6, 30) 1 7 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 4 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 8 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 10 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 12 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 14 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 16 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 18 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 20 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 22 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 24 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 26 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2323 | 00 00 00 00 00 00 00 00 | 0x00000000 1 7 28 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 0]Bigger pass win(1, 6, 4) Pass tap=28 1 7 30 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1E1E | 00 00 00 00 00 00 00 00 | 0x00000000 2 0 0 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x1616 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 2 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2120 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 4 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 [Byte 2]Bigger pass win(1, 6, 18) Pass tap=25 2 0 6 |(B3->B0) 0x2323, 0x2323, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 [Byte 2]First pass (2, 0, 6) 2 0 8 |(B3->B0) 0x2323, 0x1C1C, 0x2323, 0x2322 | 00 00 00 00 00 00 11 11 | 0x00000000 2 0 10 |(B3->B0) 0x2323, 0x1514, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 12 |(B3->B0) 0x2323, 0x1B1B, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 14 |(B3->B0) 0x2323, 0x2221, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 16 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 18 |(B3->B0) 0x2323, 0x2322, 0x2323, 0x2322 | 00 00 11 11 00 00 11 11 | 0x00000000 2 0 20 |(B3->B0) 0x2322, 0x2322, 0x2221, 0x2322 | 11 11 11 11 11 11 11 11 | 0x00000000 [Byte 1]Bigger pass win(1, 6, 28) Pass tap=28 [Byte 3]Bigger pass win(1, 6, 30) Pass tap=27 All bytes gating window pass, Done, Early break! =============================================================================== dqs input gating widnow, final delay value channel=1(2:cha, 3:chb) rank=0 =============================================================================== test2_1: 0x55000000, test2_2: 0xAA000400, test pattern: 5 dqs input gating widnow, best delay value =============================================================================== best DQS0 delay(2T, 0.5T, PI) = (1, 7, 0) best DQS1 delay(2T, 0.5T, PI) = (1, 7, 24) best DQS2 delay(2T, 0.5T, PI) = (1, 7, 11) best DQS3 delay(2T, 0.5T, PI) = (1, 7, 25) =============================================================================== best DQS0 P1 delay(2T, 0.5T, PI) = (2, 1, 0) best DQS1 P1 delay(2T, 0.5T, PI) = (2, 1, 24) best DQS2 P1 delay(2T, 0.5T, PI) = (2, 1, 11) best DQS3 P1 delay(2T, 0.5T, PI) = (2, 1, 25) =============================================================================== [DramcRxdqsGatingCal] ====Done==== ============================================================== [DATLAT] Frequency=800, Channel=1, Rank=0, use_rxtx_scan=0 ============================================================== DATLAT Default value = 0x13 5, 0xFFFFFFFF, sum=0 6, 0xFFFFFFFF, sum=0 7, 0xFFFFFFFF, sum=0 8, 0xFFFFFFFF, sum=0 9, 0xFFFFFFFF, sum=0 10, 0xFFFFFFFF, sum=0 11, 0xFFFFFFFF, sum=0 12, 0xFFFFFFFF, sum=0 13, 0xFFFFFFFF, sum=0 14, 0xFFFFFFFF, sum=0 15, 0xFFFFFFFF, sum=0 16, 0xFFFFFFFF, sum=0 17, 0x00000000, sum=1 18, 0x00000000, sum=2 19, 0x00000000, sum=3 20, 0x00000000, sum=4 21, 0x00000000, sum=5 pattern=5 first_step=17 total pass=6 best_step=19 [DramcRxdatlatCal] ====Done==== [DramcRxdqsGatingPostProcess] p->frequency 800 [DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3 TX_dly_DQSgated check: min 3 max 4, s1ChangeDQSINCTL=0 DQSINCTL=3, RANKINCTL=1, u4XRTR2R=10 [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:1 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [LJ_PHYPLL_0] waiting for K_Band [LJ_PHYPLL_0], PASS=1, FAIL=0, BAND=1A [LJ_PHYPLL_1] waiting for K_Band [LJ_PHYPLL_1], PASS=1, FAIL=0, BAND=1B [LJ_PHYPLL_2] waiting for K_Band [LJ_PHYPLL_2], PASS=1, FAIL=0, BAND=1B [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done [DramcEnterSelfRefresh] op:0 (0:exit, 1:enter) [DramcEnterSelfRefresh] Self Rresh operation done DramcModeRegInit_Everest_LP3 for Rank0 DramcModeRegInit_Everest_LP3 for Rank0 [DramcDFS] Before DVFS, disable FB_CK divide [DramcDFS] Before DVFS, disable M_CK free-run divider [DramcDFS] DVFS to type(1270) flow start DramcDFSDirectJump(shuffle start) DMA = 0 DramcDFSDirectJump(leave shuffle) DMA = 0 [DramcDFS] DVFS end [DramcDFS] After DLL lock, enable FB_CK divider End [DramcDFS] After DVFS enable M_CK free-run div EMI_CONA=20102017 EMI_CONH=0 ============================================= EMI offset:0, value:20102017 EMI offset:4, value:0 EMI offset:8, value:17283544 EMI offset:C, value:0 EMI offset:10, value:A1A0B1A EMI offset:14, value:0 EMI offset:18, value:3657587A EMI offset:1C, value:0 EMI offset:20, value:FFFF0848 EMI offset:24, value:0 EMI offset:28, value:4210000 EMI offset:2C, value:0 EMI offset:30, value:2B2B2A38 EMI offset:34, value:0 EMI offset:38, value:0 EMI offset:3C, value:0 EMI offset:40, value:8813 EMI offset:44, value:0 EMI offset:48, value:FFFF1FED EMI offset:4C, value:0 EMI offset:50, value:0 EMI offset:54, value:0 EMI offset:58, value:0 EMI offset:5C, value:0 EMI offset:60, value:63C EMI offset:64, value:0 EMI offset:68, value:0 EMI offset:6C, value:0 EMI offset:70, value:0 EMI offset:74, value:0 EMI offset:78, value:889A0C3F EMI offset:7C, value:0 EMI offset:80, value:0 EMI offset:84, value:0 EMI offset:88, value:0 EMI offset:8C, value:0 EMI offset:90, value:0 EMI offset:94, value:0 EMI offset:98, value:0 EMI offset:9C, value:0 EMI offset:A0, value:0 EMI offset:A4, value:0 EMI offset:A8, value:0 EMI offset:AC, value:0 EMI offset:B0, value:0 EMI offset:B4, value:0 EMI offset:B8, value:0 EMI offset:BC, value:0 EMI offset:C0, value:0 EMI offset:C4, value:0 EMI offset:C8, value:0 EMI offset:CC, value:0 EMI offset:D0, value:CFCFCFCF EMI offset:D4, value:0 EMI offset:D8, value:CFCFCFCF EMI offset:DC, value:0 EMI offset:E0, value:33433343 EMI offset:E4, value:0 EMI offset:E8, value:62027 EMI offset:EC, value:0 EMI offset:F0, value:38460000 EMI offset:F4, value:0 EMI offset:F8, value:0 EMI offset:FC, value:0 EMI offset:100, value:7F807048 EMI offset:104, value:0 EMI offset:108, value:7F807F40 EMI offset:10C, value:0 EMI offset:110, value:A0A070D7 EMI offset:114, value:0 EMI offset:118, value:70C5 EMI offset:11C, value:0 EMI offset:120, value:40306045 EMI offset:124, value:0 EMI offset:128, value:A0A070D8 EMI offset:12C, value:0 EMI offset:130, value:A0A07042 EMI offset:134, value:4000 EMI offset:138, value:2010704D EMI offset:13C, value:0 EMI offset:140, value:20407188 EMI offset:144, value:20406188 EMI offset:148, value:9719595E EMI offset:14C, value:9719595E EMI offset:150, value:64F3FC79 EMI offset:154, value:64F3FC79 EMI offset:158, value:FF01FF00 EMI offset:15C, value:0 Settings after calibration ... === [DramcRunTimeConfig] === HW_GATING: ON DFS_HW_SYNC_GATING_TRACKING: OFF ZQCS_ENABLE: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON SPM_CONTROL_AFTERK: ON TEMP_SENSOR_ENABLE: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x46000000) 0:dram_rank_size:80000000 dram_rank_size[0] = 0x80000000 dram_rank_size[1] = 0x0 dram_rank_size[2] = 0x0 dram_rank_size[3] = 0x0 RGU rgu_dram_reserved:MTK_WDT_MODE(2200005D) [Dram_Buffer] dram_buf_t size: 0x9C280 [Dram_Buffer] part_hdr_t size: 0x200 [Dram_Buffer] sizeof(boot_arg_t): 0xD00 [Dram_Buffer] g_dram_buf start addr: 0x44800000 [Dram_Buffer] g_dram_buf->msdc_gpd_pool start addr: 0x4489C1C0 [Dram_Buffer] g_dram_buf->msdc_bd_pool start addr: 0x4489C200 RAM_CONSOLE using SRAM RAM_CONSOLE start: 0x12D000, size: 0xC00, sig: 0x43474244 RAM_CONSOLE preloader last status: 0x0 0x0 0x0 RAM_CONSOLE wdt status (0x5)=0x5 [msdc_init]: msdc0 Host controller intialization start [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [msdc_init]: msdc0 Host controller intialization done [SD0] Switch to High-Speed mode! [SD0] Switch to SDR buswidth [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [SD0] Switch to High-Speed mode! [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0) [mmc_init_card]: finish successfully [PLFM] Init Boot Device: OK(0) 0:dram_rank_size:80000000 0:dram_rank_size:80000000 orig_dram_info[0] start: 0x0000000040000000, size: 0x0000000080000000 [Enable 4GB Support] 4GB_flag 0x0 total_dram_size: 0x0000000080000000, max_dram_size: 0xFFFFFFFFFFFFFFFF [GPT_PL]Parsing Primary GPT now... [GPT_PL][0]name=recovery, part_id=8, start_sect=0x40, nr_sects=0x8000 [GPT_PL][1]name=para, part_id=8, start_sect=0x8040, nr_sects=0x400 [GPT_PL][2]name=expdb, part_id=8, start_sect=0x8440, nr_sects=0x5000 [GPT_PL][3]name=frp, part_id=8, start_sect=0xD440, nr_sects=0x800 [GPT_PL][4]name=nvcfg, part_id=8, start_sect=0xDC40, nr_sects=0x4000 [GPT_PL][5]name=nvdata, part_id=8, start_sect=0x11C40, nr_sects=0x10000 [GPT_PL][6]name=metadata, part_id=8, start_sect=0x21C40, nr_sects=0x10000 [GPT_PL][7]name=protect1, part_id=8, start_sect=0x31C40, nr_sects=0x4000 [GPT_PL][8]name=protect2, part_id=8, start_sect=0x35C40, nr_sects=0x63C0 [GPT_PL][9]name=seccfg, part_id=8, start_sect=0x3C000, nr_sects=0x4000 [GPT_PL][10]name=oemkeystore, part_id=8, start_sect=0x40000, nr_sects=0x1000 [GPT_PL][11]name=proinfo, part_id=8, start_sect=0x41000, nr_sects=0x1800 [GPT_PL][12]name=md1img, part_id=8, start_sect=0x42800, nr_sects=0xC000 [GPT_PL][13]name=md1dsp, part_id=8, start_sect=0x4E800, nr_sects=0x2000 [GPT_PL][14]name=md1arm7, part_id=8, start_sect=0x50800, nr_sects=0x1800 [GPT_PL][15]name=md3img, part_id=8, start_sect=0x52000, nr_sects=0x2800 [GPT_PL][16]name=scp1, part_id=8, start_sect=0x54800, nr_sects=0x800 [GPT_PL][17]name=scp2, part_id=8, start_sect=0x55000, nr_sects=0x800 [GPT_PL][18]name=nvram, part_id=8, start_sect=0x55800, nr_sects=0x2800 [GPT_PL][19]name=lk, part_id=8, start_sect=0x58000, nr_sects=0x400 [GPT_PL][20]name=lk2, part_id=8, start_sect=0x58400, nr_sects=0x400 [GPT_PL][21]name=boot, part_id=8, start_sect=0x58800, nr_sects=0x8000 [GPT_PL][22]name=logo, part_id=8, start_sect=0x60800, nr_sects=0x4000 [GPT_PL][23]name=tee1, part_id=8, start_sect=0x64800, nr_sects=0x2800 [GPT_PL][24]name=tee2, part_id=8, start_sect=0x67000, nr_sects=0x2800 [GPT_PL][25]name=keystore, part_id=8, start_sect=0x69800, nr_sects=0x6800 [GPT_PL][26]name=system, part_id=8, start_sect=0x70000, nr_sects=0x500000 [GPT_PL][27]name=cache, part_id=8, start_sect=0x570000, nr_sects=0xD8000 [GPT_PL][28]name=userdata, part_id=8, start_sect=0x648000, nr_sects=0x83FFDF [GPT_PL][29]name=flashinfo, part_id=8, start_sect=0xE87FDF, nr_sects=0x8000 [GPT_PL]Success to find valid GPT. LOG_STORE:sram->sig value 0xABCD1234! LOG_STORE:log_to_emmc function flag 0x27! LOG_STORE: expdb partition add 0x8440, size 0x5000, blk size 0x200! LOG_STORE:lk size 0x0, pl size 0x685B! LOG_STORE:log_to_emmc add 0x1888000! LOG_STORE:log_to_emmc write size 0x6A00, ret value 0x0! mblock[0].start: 0x0000000040000000, sz: 0x0000000080000000, limit: 0x00000000C0000000, max_addr: 0x0000000000000000, max_rank: 0, target: -1, mblock[].rank: 0, reserved_addr: 0x00000000BFFE0000,reserved_size: 0x0000000000020000 mblock_reserve dbg[0]: 0, 1, 1, 1, 1 mblock_reserve: 00000000BFFE0000 - 00000000C0000000 from mblock 0 mblock-debug[0].start: 0x0000000040000000, sz: 0x000000007FFE0000 LOG_STORE:sram_header 0x12DC00,sig 0xABCD1234, sram_dram_buff 0x12DC18, buf_addr 0xBFFE0000, pl_buff_header 0xBFFE0000! [PART] blksz: 512B [PART] [0x0000000000008000-0x0000000001007FFF] "recovery" (32768 blocks) [PART] [0x0000000001008000-0x0000000001087FFF] "para" (1024 blocks) [PART] [0x0000000001088000-0x0000000001A87FFF] "expdb" (20480 blocks) [PART] [0x0000000001A88000-0x0000000001B87FFF] "frp" (2048 blocks) [PART] [0x0000000001B88000-0x0000000002387FFF] "nvcfg" (16384 blocks) [PART] [0x0000000002388000-0x0000000004387FFF] "nvdata" (65536 blocks) [PART] [0x0000000004388000-0x0000000006387FFF] "metadata" (65536 blocks) [PART] [0x0000000006388000-0x0000000006B87FFF] "protect1" (16384 blocks) [PART] [0x0000000006B88000-0x00000000077FFFFF] "protect2" (25536 blocks) [PART] [0x0000000007800000-0x0000000007FFFFFF] "seccfg" (16384 blocks) [PART] [0x0000000008000000-0x00000000081FFFFF] "oemkeystore" (4096 blocks) [PART] [0x0000000008200000-0x00000000084FFFFF] "proinfo" (6144 blocks) [PART] [0x0000000008500000-0x0000000009CFFFFF] "md1img" (49152 blocks) [PART] [0x0000000009D00000-0x000000000A0FFFFF] "md1dsp" (8192 blocks) [PART] [0x000000000A100000-0x000000000A3FFFFF] "md1arm7" (6144 blocks) [PART] [0x000000000A400000-0x000000000A8FFFFF] "md3img" (10240 blocks) [PART] [0x000000000A900000-0x000000000A9FFFFF] "scp1" (2048 blocks) [PART] [0x000000000AA00000-0x000000000AAFFFFF] "scp2" (2048 blocks) [PART] [0x000000000AB00000-0x000000000AFFFFFF] "nvram" (10240 blocks) [PART] [0x000000000B000000-0x000000000B07FFFF] "lk" (1024 blocks) [PART] [0x000000000B080000-0x000000000B0FFFFF] "lk2" (1024 blocks) [PART] [0x000000000B100000-0x000000000C0FFFFF] "boot" (32768 blocks) [PART] [0x000000000C100000-0x000000000C8FFFFF] "logo" (16384 blocks) [PART] [0x000000000C900000-0x000000000CDFFFFF] "tee1" (10240 blocks) [PART] [0x000000000CE00000-0x000000000D2FFFFF] "tee2" (10240 blocks) [PART] [0x000000000D300000-0x000000000DFFFFFF] "keystore" (26624 blocks) [PART] [0x000000000E000000-0x00000000ADFFFFFF] "system" (5242880 blocks) [PART] [0x00000000AE000000-0x00000000C8FFFFFF] "cache" (884736 blocks) [PART] [0x00000000C9000000-0x00000001D0FFBDFF] "userdata" (8650719 blocks) [PART] [0x00000001D0FFBE00-0x00000001D1FFBDFF] "flashinfo" (32768 blocks) €€€€€€€€€€€[BLDR] Tool connection is unlocked platform_vusb_on VUSB33 is on platform_vusb_on VA10 is on platform_vusb_on VA10 select to 0.95V step A2 : Standard USB Host! [PLFM] USB cable in [TOOL] USB enum timeout (Yes), handshake timeout(Yes) [TOOL] Enumeration(Start) HS is detected HS is detected [TOOL] Enumeration(End): OK 391ms [TOOL] : usb listen timeout [TOOL] cannot detect tools! [TOOL] listen ended, receive size:0! [TOOL] wait sync time 150ms->5ms [TOOL] receieved data: () Device APC domain init setup: Domain Setup (0x0) Domain Setup (0x0) Domain Setup (0x0) Domain Setup (0x0) Domain Setup (0x0) Device APC domain after setup: Domain Setup (0x0) Domain Setup (0x10003000) Domain Setup (0x5511011) Domain Setup (0x260) Domain Setup (0x6) (B)tz_dapc_sec_init is 0x0 (E)tz_dapc_sec_init is 0x0 (E)MAS0=0x20 (E)MAS1=0x0 mblock[0].start: 0x0000000040000000, sz: 0x000000007FFE0000, limit: 0x00000000C0000000, max_addr: 0x0000000000000000, max_rank: 0, target: -1, mblock[].rank: 0, reserved_addr: 0x00000000BFFA0000,reserved_size: 0x0000000000040000 mblock_reserve dbg[0]: 0, 1, 1, 1, 1 mblock_reserve: 00000000BFFA0000 - 00000000BFFE0000 from mblock 0 mblock-debug[0].start: 0x0000000040000000, sz: 0x000000007FFA0000 [BLDR] lk active = 0, lk2 active = 0 [BLDR] Loading LK Partition... [PART] partition hdr (1) [PART] Image with part header [PART] name : lk [PART] addr : FFFFFFFFh mode : -1 [PART] size : 415132 [PART] magic: 58881688h [PART] load "lk" from 0x000000000B000200 (dev) to 0x46000000 (mem) [SUCCESS] [PART] load speed: 10667KB/s, 415132 bytes, 38ms LK addr: 0x46000000, size: 0x6559C [PART] partition hdr (1) [PART] Image with part header [PART] name : atf [PART] addr : FFFFFFFFh mode : 0 [PART] size : 81408 [PART] magic: 58881688h [PART] load "tee1" from 0x000000000C900200 (dev) to 0x1005C0 (mem) [SUCCESS] [PART] load speed: 8833KB/s, 81408 bytes, 9ms [BLDR] bldr load tee part ret=0x0, addr=0x1005C0 g_da9214_hw_exist=1 [PICACHU] ---- cluster 'FY-L' ---- [PICACHU] scenario#2: ac on [PICACHU] ---- cluster 'FY-B' ---- [PICACHU] scenario#2: ac on [PLFM] boot to LK by ATAG. [xxxx1][preloader]first_volt = 0x68 [xxxx1][preloader]second_volt = 0x58 [xxxx1][preloader]third_volt = 0x48 [xxxx1][preloader]have_550 = 0x0 BOOT_REASON: 4 BOOT_MODE: 0 META_COM TYPE: 0 META_COM ID: 0 META_COM PORT: 285220864 LOG_COM PORT: 285220864 LOG_COM BAUD: 921600 LOG_COM EN: 1 MEM_NUM: 1 MEM_SIZE: 0x7FFA0000 mblock num: 0x1 mblock start: 0x0000000040000000 mblock size: 0x000000007FFA0000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 mblock start: 0x0000000000000000 mblock size: 0x0000000000000000 mblock rank: 0x0 orig_dram num: 0x1 orig_dram start: 0x0000000040000000 orig_dram size: 0x0000000080000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 orig_dram start: 0x0000000000000000 orig_dram size: 0x0000000000000000 lca start: 0x0000000000000000 lca size: 0x0000000000000000 tee start: 0x00000000BFFA0000 tee size: 0x0000000000040000 MD_INFO: 0x0 MD_INFO: 0x0 MD_INFO: 0x0 MD_INFO: 0x0 BOOT_TIME: 5176 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 DA_INFO: 0x0 SEC_INFO: 0x0 SEC_INFO: 0x0 PART_NUM: 2 PART_INFO: 0x44879A84 EFLAG: 0 DDR_RESERVE: 0 DDR_RESERVE: 0 DRAM_BUF: 639616 SRAM start: 0x12A000 SRAM size: 0x6000 [TZ_INIT] atf_log_port : 0x11002000 [TZ_INIT] atf_log_baudrate : 0xE1000 [TZ_INIT] atf_irq_num : 325 [TZ_INIT] ATF log buffer start : 0xBFFA0000 [TZ_INIT] ATF log buffer size : 0x40000 [TZ_INIT] ATF aee buffer start : 0xBFFDC000 [TZ_INIT] ATF aee buffer size : 0x4000 [BLDR] Others, jump to ATF [BLDR] jump to 0x46000000 [BLDR] <0x46000000>=0xEA000007 [BLDR] <0x46000004>=0xEA009293 [TZ_SEC_CFG] SRAMROM Secure Addr 0x2A000 [TZ_SEC_CFG] SRAMROM Secure Control 0x40000000 [TZ_SEC_CFG] SRAMROM Secure Control 0x40000B69 [TZ_SEC_CFG] SRAMROM Secure Control 0x51680B69 [TZ_INIT] ATF entry addr, dram addr: 0x101000, 0x44600000 [TZ_EMI_MPU] MPU [0x44600000-0x4460FFFF] [TZ_INIT] set secure memory protection : 0x44600000, 0x4460FFFF (1) [TZ_INIT] Jump to ATF, then 0x46000000 [ATF](0)[0.7]CPUxGPT reg(201) [ATF](0)[0.327]BL33 boot argument location=0x4489c240 [ATF](0)[0.964]BL33 boot argument size=0xd00 [ATF](0)[0.1485]BL33 start addr=0x46000000 [ATF](0)[0.1984]teearg addr=0x100000 [ATF](0)[0.2413]atf_magic=0x4d415446 [ATF](0)[0.2842]tee_support=0x0 [ATF](0)[0.3212]tee_entry=0x0 [ATF](0)[0.3558]tee_boot_arg_addr=0x100100 [ATF](0)[0.4057]atf_log_port=0x11002000 [ATF](0)[0.4521]atf_log_baudrate=0xe1000 [ATF](0)[0.4996]atf_log_buf_start=0xbffa0000 [ATF](0)[0.5518]atf_log_buf_size=0x40000 [ATF](0)[0.5992]atf_aee_debug_buf_start=0xbffdc000 [ATF](0)[0.6584]atf_aee_debug_buf_size=0x4000 [ATF](0)[0.7116]atf_irq_num=325 [ATF](0)[0.7487]BL33_START_ADDRESS=0x46000000 [ATF](0)[0.8020]atf chip_code[279] [ATF](0)[0.8403]atf chip_ver[0] [ATF](0)[0.8770]###@@@ MP0_MISC_CONFIG3:0x000f0000 @@@### [ATF](0)[0.9424]###@@@ MP0_MISC_CONFIG3:0x000fe000 @@@### [ATF](0)[0.10085]mmap atf buffer : 0xbffa0000, 0x40000 [ATF](0)[0.10847]mmap atf buffer (force 2MB aligned): 0xbfe00000, 0x200000 [ATF](0)[0.11708]###@@@ CPUSYS1 OFF @@@### [ATF](0)[0.12182]power_off_little_cl cl:1 [ATF](0)[0.12667]INFRA_TOPAXI_PROTECTEN1 (0x10001234):0x00000222 [ATF](0)[0.13423]end NOTICE: BL3-1: v1.0(debug):3eddbd5 NOTICE: BL3-1: Built : 01:49:35, Jul 10 2016 [ATF](0)[0.16430]crash flag: 0x41544641 [ATF](0)[0.16871]sta=0x0 int=0xff8 [ATF](0)[0.17269]is_power_on_boot: false [ATF](0)[0.17881]atf_buf_addr : 0xbffa0100 [ATF](0)[0.18326]atf_buf_size : 0x29f00 [ATF](0)[0.18767]dump crashlog [ATF](0)[0.19112]atf_crash_log_addr: 0xbffca000 [ATF](0)[0.19639]dump_ret=576. [ATF](0)[0.22085]mt_log_setup - atf_buf_addr : 0xbffa0100 [ATF](0)[0.22690]mt_log_setup - atf_buf_size : 0x29f00 [ATF](0)[0.23294]mt_log_setup - atf_write_pos : 0xbffa0100 [ATF](0)[0.23940]mt_log_setup - atf_read_pos : 0xbffa0100 [ATF](0)[0.24575]mt_log_setup - atf_buf_lock : 0x0 [ATF](0)[0.25135]mt_log_setup - mt_log_buf_end : 0xbffc9fff [ATF](0)[0.25792]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000 [ATF](0)[0.26503]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000 [ATF](0)[0.27256]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0xa000 [ATF](0)[0.27924]mt_log_setup - PLATFORM_CORE_COUNT : 0xa [ATF](0)[0.28560]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x0(Hi), 0xbffd2000(Low) [ATF](0)[0.29539]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x0(Hi), 0xbffd3000(Low) [ATF](0)[0.30520]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x0(Hi), 0xbffd4000(Low) [ATF](0)[0.31499]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x0(Hi), 0xbffd5000(Low) [ATF](0)[0.32480]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x0(Hi), 0xbffd6000(Low) [ATF](0)[0.33459]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x0(Hi), 0xbffd7000(Low) [ATF](0)[0.34439]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x0(Hi), 0xbffd8000(Low) [ATF](0)[0.35420]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x0(Hi), 0xbffd9000(Low) [ATF](0)[0.36400]mt_log_setup - atf_except_write_pos_per_cpu[8]: 0x0(Hi), 0xbffda000(Low) [ATF](0)[0.37379]mt_log_setup - atf_except_write_pos_per_cpu[9]: 0x0(Hi), 0xbffdb000(Low) [ATF](0)[0.38360]mt_log_setup - atf_crash_flag : 0x41544641 [ATF](0)[0.39017]mt_log_setup - atf_crash_log_addr : 0xbffca000 [ATF](0)[0.39717]mt_log_setup - atf_crash_log_size : 0x8000 [ATF](0)[0.40374]ATF log service is registered (0xbffa0000, aee:0xbffdc000) [ATF](0)[0.41204]BL3-1: v1.0(debug):3eddbd5 [ATF](0)[0.41688]BL3-1: Built : 01:49:35, Jul 10 2016 INFO: BL3-1: Initializing runtime services [ATF](0)[0.42857][BL31] Jump to FIQD for initialization! INFO: BL3-1: Preparing for EL3 exit to normal world, LK INFO: BL3-1: Next image address = 0x46000000 INFO: BL3-1: Next image spsr = 0x1d3 [ATF](0)[0.45083][BL31] Final dump! [LOG_STORE:log_store_init. LOG_STORE:sram buff header 0x12dc00,buff address 0xbffe0000, sig 0xcdab3412, buff_size 0x20000, pl 0x69e1 : 0x28, lk size0x0 : 0x28! LOG_STORE:value S. LOG_STORE: buff ready. 0] [PWRAP] pwrap_init_lk [0] [PWRAP] is_pwrap_init_done 1 [0] [BATTERY] /QON counter still counting... [10] platform_init() [20] [msdc_init]: msdc0 Host controller intialization start [20] [info][msdc_set_startbit 489] read data start bit at rising edge [20] [info][msdc_config_clksrc] input clock is 400000kHz [20] [SD0] Bus Width: 1 [20] [info][msdc_config_clksrc] input clock is 400000kHz [20] [info][msdc_set_startbit 489] read data start bit at rising edge [20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [20] [msdc_init]: msdc0 Host controller intialization done [20] [mmc_init]: msdc0 start mmc_init_card() [20] [mmc_init_card]: start [120] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 4MB, csd.write_prot_grpsz = 7,csd.erase_sctsz = 1024 [120] [mmc_decode_ext_csd]: mmc_set_wp_size 4MB [120] [SD0] Switch to High-Speed mode! [120] [SD0] Switch to SDR buswidth [140] [info][msdc_config_clksrc] input clock is 400000kHz [140] [info][msdc_set_startbit 489] read data start bit at rising edge [140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0) [140] [SD0] Bus Width: 8 [140] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0) [140] [mmc_init_mem_card 3543][SD0] Initialized, eMMC50 [140] before host->cur_bus_clk(259740) [140] [SD0] Switch to High-Speed mode! [140] [info][msdc_config_clksrc] input clock is 400000kHz [140] [info][msdc_set_startbit 489] read data start bit at rising edge [140] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0) [160] host->cur_bus_clk(50000000) [160] [mmc_init_card]: finish successfully [160] [mt_part_register_device] [160] [GPT_LK]Parsing Primary GPT now... [160] [GPT_LK][0]name=recovery, part_id=8, start_sect=0x40, nr_sects=0x8000 [160] [GPT_LK][1]name=para, part_id=8, start_sect=0x8040, nr_sects=0x400 [160] [GPT_LK][2]name=expdb, part_id=8, start_sect=0x8440, nr_sects=0x5000 [160] [GPT_LK][3]name=frp, part_id=8, start_sect=0xd440, nr_sects=0x800 [160] [GPT_LK][4]name=nvcfg, part_id=8, start_sect=0xdc40, nr_sects=0x4000 [160] [GPT_LK][5]name=nvdata, part_id=8, start_sect=0x11c40, nr_sects=0x10000 [180] [GPT_LK][6]name=metadata, part_id=8, start_sect=0x21c40, nr_sects=0x10000 [180] [GPT_LK][7]name=protect1, part_id=8, start_sect=0x31c40, nr_sects=0x4000 [180] [GPT_LK][8]name=protect2, part_id=8, start_sect=0x35c40, nr_sects=0x63c0 [180] [GPT_LK][9]name=seccfg, part_id=8, start_sect=0x3c000, nr_sects=0x4000 [180] [GPT_LK][10]name=oemkeystore, part_id=8, start_sect=0x40000, nr_sects=0x1000 [180] [GPT_LK][11]name=proinfo, part_id=8, start_sect=0x41000, nr_sects=0x1800 [180] [GPT_LK][12]name=md1img, part_id=8, start_sect=0x42800, nr_sects=0xc000 [180] [GPT_LK][13]name=md1dsp, part_id=8, start_sect=0x4e800, nr_sects=0x2000 [180] [GPT_LK][14]name=md1arm7, part_id=8, start_sect=0x50800, nr_sects=0x1800 [180] [GPT_LK][15]name=md3img, part_id=8, start_sect=0x52000, nr_sects=0x2800 [180] [GPT_LK][16]name=scp1, part_id=8, start_sect=0x54800, nr_sects=0x800 [200] [GPT_LK][17]name=scp2, part_id=8, start_sect=0x55000, nr_sects=0x800 [200] [GPT_LK][18]name=nvram, part_id=8, start_sect=0x55800, nr_sects=0x2800 [200] [GPT_LK][19]name=lk, part_id=8, start_sect=0x58000, nr_sects=0x400 [200] [GPT_LK][20]name=lk2, part_id=8, start_sect=0x58400, nr_sects=0x400 [200] [GPT_LK][21]name=boot, part_id=8, start_sect=0x58800, nr_sects=0x8000 [200] [GPT_LK][22]name=logo, part_id=8, start_sect=0x60800, nr_sects=0x4000 [200] [GPT_LK][23]name=tee1, part_id=8, start_sect=0x64800, nr_sects=0x2800 [200] [GPT_LK][24]name=tee2, part_id=8, start_sect=0x67000, nr_sects=0x2800 [200] [GPT_LK][25]name=keystore, part_id=8, start_sect=0x69800, nr_sects=0x6800 [200] [GPT_LK][26]name=system, part_id=8, start_sect=0x70000, nr_sects=0x500000 [200] [GPT_LK][27]name=cache, part_id=8, start_sect=0x570000, nr_sects=0xd8000 [200] [GPT_LK][28]name=userdata, part_id=8, start_sect=0x648000, nr_sects=0x83ffdf [220] [GPT_LK][29]name=flashinfo, part_id=8, start_sect=0xe87fdf, nr_sects=0x8000 [220] [GPT_LK]Success to find valid GPT. [220] [SD0] boot device found [220] [PART_LK][get_part] para [220] [LK_BOOT] Load 'para' partition to 0x4607F344 (6144 bytes in 3 ms) [220] [PART_LK][get_part] boot [220] [LK_BOOT] Load 'boot' partition to 0x46900000 (608 bytes in 2 ms) [220] Warning! No bootopt info! [220] [PART_LK][get_part] boot [400] [LK_BOOT] Load 'boot' partition to 0x46900000 (3688448 bytes in 83 ms)